// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
// Date        : Thu Jun 20 02:34:56 2024
// Host        : lsin-ThinkStation-K-C2490 running 64-bit Ubuntu 23.10
// Command     : write_verilog -force -mode funcsim
//               /home/lsin/vivado_projects/lab2rev/part4/part3.gen/sources_1/bd/design_1/ip/design_1_PWM_0_0/design_1_PWM_0_0_sim_netlist.v
// Design      : design_1_PWM_0_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xczu5eg-sfvc784-1-e
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "design_1_PWM_0_0,PWM_v1_0,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "PWM_v1_0,Vivado 2023.2" *) 
(* NotValidForBitStream *)
module design_1_PWM_0_0
   (PWM_Out,
    pwm_axi_aclk,
    pwm_axi_aresetn,
    pwm_axi_awaddr,
    pwm_axi_awprot,
    pwm_axi_awvalid,
    pwm_axi_awready,
    pwm_axi_wdata,
    pwm_axi_wstrb,
    pwm_axi_wvalid,
    pwm_axi_wready,
    pwm_axi_bresp,
    pwm_axi_bvalid,
    pwm_axi_bready,
    pwm_axi_araddr,
    pwm_axi_arprot,
    pwm_axi_arvalid,
    pwm_axi_arready,
    pwm_axi_rdata,
    pwm_axi_rresp,
    pwm_axi_rvalid,
    pwm_axi_rready);
  output [3:0]PWM_Out;
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 PWM_AXI_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME PWM_AXI_CLK, ASSOCIATED_BUSIF PWM_AXI, ASSOCIATED_RESET pwm_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_zynq_ultra_ps_e_0_0_pl_clk0, INSERT_VIP 0" *) input pwm_axi_aclk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 PWM_AXI_RST RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME PWM_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input pwm_axi_aresetn;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI AWADDR" *) input [4:0]pwm_axi_awaddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI AWPROT" *) input [2:0]pwm_axi_awprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI AWVALID" *) input pwm_axi_awvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI AWREADY" *) output pwm_axi_awready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI WDATA" *) input [31:0]pwm_axi_wdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI WSTRB" *) input [3:0]pwm_axi_wstrb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI WVALID" *) input pwm_axi_wvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI WREADY" *) output pwm_axi_wready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI BRESP" *) output [1:0]pwm_axi_bresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI BVALID" *) output pwm_axi_bvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI BREADY" *) input pwm_axi_bready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI ARADDR" *) input [4:0]pwm_axi_araddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI ARPROT" *) input [2:0]pwm_axi_arprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI ARVALID" *) input pwm_axi_arvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI ARREADY" *) output pwm_axi_arready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI RDATA" *) output [31:0]pwm_axi_rdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI RRESP" *) output [1:0]pwm_axi_rresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI RVALID" *) output pwm_axi_rvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PWM_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME PWM_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 5, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 5, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_1_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input pwm_axi_rready;

  wire \<const0> ;
  wire [3:0]PWM_Out;
  wire pwm_axi_aclk;
  wire [4:0]pwm_axi_araddr;
  wire pwm_axi_aresetn;
  wire pwm_axi_arready;
  wire pwm_axi_arvalid;
  wire [4:0]pwm_axi_awaddr;
  wire pwm_axi_awready;
  wire pwm_axi_awvalid;
  wire pwm_axi_bready;
  wire pwm_axi_bvalid;
  wire [31:0]pwm_axi_rdata;
  wire pwm_axi_rready;
  wire pwm_axi_rvalid;
  wire [31:0]pwm_axi_wdata;
  wire pwm_axi_wready;
  wire [3:0]pwm_axi_wstrb;
  wire pwm_axi_wvalid;

  assign pwm_axi_bresp[1] = \<const0> ;
  assign pwm_axi_bresp[0] = \<const0> ;
  assign pwm_axi_rresp[1] = \<const0> ;
  assign pwm_axi_rresp[0] = \<const0> ;
  GND GND
       (.G(\<const0> ));
  design_1_PWM_0_0_PWM_v1_0 inst
       (.PWM_Out(PWM_Out),
        .S_AXI_ARREADY(pwm_axi_arready),
        .S_AXI_AWREADY(pwm_axi_awready),
        .S_AXI_WREADY(pwm_axi_wready),
        .pwm_axi_aclk(pwm_axi_aclk),
        .pwm_axi_araddr(pwm_axi_araddr[4:2]),
        .pwm_axi_aresetn(pwm_axi_aresetn),
        .pwm_axi_arvalid(pwm_axi_arvalid),
        .pwm_axi_awaddr(pwm_axi_awaddr[4:2]),
        .pwm_axi_awvalid(pwm_axi_awvalid),
        .pwm_axi_bready(pwm_axi_bready),
        .pwm_axi_bvalid(pwm_axi_bvalid),
        .pwm_axi_rdata(pwm_axi_rdata),
        .pwm_axi_rready(pwm_axi_rready),
        .pwm_axi_rvalid(pwm_axi_rvalid),
        .pwm_axi_wdata(pwm_axi_wdata),
        .pwm_axi_wstrb(pwm_axi_wstrb),
        .pwm_axi_wvalid(pwm_axi_wvalid));
endmodule

(* ORIG_REF_NAME = "PWM_Logic" *) 
module design_1_PWM_0_0_PWM_Logic
   (PWM_Out,
    Q,
    \PWM_Out_reg[0]_0 ,
    \PWM_Out_reg[1]_0 ,
    \PWM_Out_reg[2]_0 ,
    \PWM_Out_reg[3]_0 ,
    pwm_axi_aclk);
  output [3:0]PWM_Out;
  input [31:0]Q;
  input [31:0]\PWM_Out_reg[0]_0 ;
  input [31:0]\PWM_Out_reg[1]_0 ;
  input [31:0]\PWM_Out_reg[2]_0 ;
  input [31:0]\PWM_Out_reg[3]_0 ;
  input pwm_axi_aclk;

  wire [3:0]PWM_Out;
  wire PWM_Out0;
  wire PWM_Out0_carry__0_i_10_n_0;
  wire PWM_Out0_carry__0_i_11_n_0;
  wire PWM_Out0_carry__0_i_12_n_0;
  wire PWM_Out0_carry__0_i_13_n_0;
  wire PWM_Out0_carry__0_i_14_n_0;
  wire PWM_Out0_carry__0_i_15_n_0;
  wire PWM_Out0_carry__0_i_16_n_0;
  wire PWM_Out0_carry__0_i_1_n_0;
  wire PWM_Out0_carry__0_i_2_n_0;
  wire PWM_Out0_carry__0_i_3_n_0;
  wire PWM_Out0_carry__0_i_4_n_0;
  wire PWM_Out0_carry__0_i_5_n_0;
  wire PWM_Out0_carry__0_i_6_n_0;
  wire PWM_Out0_carry__0_i_7_n_0;
  wire PWM_Out0_carry__0_i_8_n_0;
  wire PWM_Out0_carry__0_i_9_n_0;
  wire PWM_Out0_carry__0_n_0;
  wire PWM_Out0_carry__0_n_1;
  wire PWM_Out0_carry__0_n_2;
  wire PWM_Out0_carry__0_n_3;
  wire PWM_Out0_carry__0_n_4;
  wire PWM_Out0_carry__0_n_5;
  wire PWM_Out0_carry__0_n_6;
  wire PWM_Out0_carry__0_n_7;
  wire PWM_Out0_carry_i_10_n_0;
  wire PWM_Out0_carry_i_11_n_0;
  wire PWM_Out0_carry_i_12_n_0;
  wire PWM_Out0_carry_i_13_n_0;
  wire PWM_Out0_carry_i_14_n_0;
  wire PWM_Out0_carry_i_15_n_0;
  wire PWM_Out0_carry_i_16_n_0;
  wire PWM_Out0_carry_i_1_n_0;
  wire PWM_Out0_carry_i_2_n_0;
  wire PWM_Out0_carry_i_3_n_0;
  wire PWM_Out0_carry_i_4_n_0;
  wire PWM_Out0_carry_i_5_n_0;
  wire PWM_Out0_carry_i_6_n_0;
  wire PWM_Out0_carry_i_7_n_0;
  wire PWM_Out0_carry_i_8_n_0;
  wire PWM_Out0_carry_i_9_n_0;
  wire PWM_Out0_carry_n_0;
  wire PWM_Out0_carry_n_1;
  wire PWM_Out0_carry_n_2;
  wire PWM_Out0_carry_n_3;
  wire PWM_Out0_carry_n_4;
  wire PWM_Out0_carry_n_5;
  wire PWM_Out0_carry_n_6;
  wire PWM_Out0_carry_n_7;
  wire \PWM_Out0_inferred__0/i__carry__0_n_0 ;
  wire \PWM_Out0_inferred__0/i__carry__0_n_1 ;
  wire \PWM_Out0_inferred__0/i__carry__0_n_2 ;
  wire \PWM_Out0_inferred__0/i__carry__0_n_3 ;
  wire \PWM_Out0_inferred__0/i__carry__0_n_4 ;
  wire \PWM_Out0_inferred__0/i__carry__0_n_5 ;
  wire \PWM_Out0_inferred__0/i__carry__0_n_6 ;
  wire \PWM_Out0_inferred__0/i__carry__0_n_7 ;
  wire \PWM_Out0_inferred__0/i__carry_n_0 ;
  wire \PWM_Out0_inferred__0/i__carry_n_1 ;
  wire \PWM_Out0_inferred__0/i__carry_n_2 ;
  wire \PWM_Out0_inferred__0/i__carry_n_3 ;
  wire \PWM_Out0_inferred__0/i__carry_n_4 ;
  wire \PWM_Out0_inferred__0/i__carry_n_5 ;
  wire \PWM_Out0_inferred__0/i__carry_n_6 ;
  wire \PWM_Out0_inferred__0/i__carry_n_7 ;
  wire \PWM_Out0_inferred__1/i__carry__0_n_0 ;
  wire \PWM_Out0_inferred__1/i__carry__0_n_1 ;
  wire \PWM_Out0_inferred__1/i__carry__0_n_2 ;
  wire \PWM_Out0_inferred__1/i__carry__0_n_3 ;
  wire \PWM_Out0_inferred__1/i__carry__0_n_4 ;
  wire \PWM_Out0_inferred__1/i__carry__0_n_5 ;
  wire \PWM_Out0_inferred__1/i__carry__0_n_6 ;
  wire \PWM_Out0_inferred__1/i__carry__0_n_7 ;
  wire \PWM_Out0_inferred__1/i__carry_n_0 ;
  wire \PWM_Out0_inferred__1/i__carry_n_1 ;
  wire \PWM_Out0_inferred__1/i__carry_n_2 ;
  wire \PWM_Out0_inferred__1/i__carry_n_3 ;
  wire \PWM_Out0_inferred__1/i__carry_n_4 ;
  wire \PWM_Out0_inferred__1/i__carry_n_5 ;
  wire \PWM_Out0_inferred__1/i__carry_n_6 ;
  wire \PWM_Out0_inferred__1/i__carry_n_7 ;
  wire \PWM_Out0_inferred__2/i__carry__0_n_1 ;
  wire \PWM_Out0_inferred__2/i__carry__0_n_2 ;
  wire \PWM_Out0_inferred__2/i__carry__0_n_3 ;
  wire \PWM_Out0_inferred__2/i__carry__0_n_4 ;
  wire \PWM_Out0_inferred__2/i__carry__0_n_5 ;
  wire \PWM_Out0_inferred__2/i__carry__0_n_6 ;
  wire \PWM_Out0_inferred__2/i__carry__0_n_7 ;
  wire \PWM_Out0_inferred__2/i__carry_n_0 ;
  wire \PWM_Out0_inferred__2/i__carry_n_1 ;
  wire \PWM_Out0_inferred__2/i__carry_n_2 ;
  wire \PWM_Out0_inferred__2/i__carry_n_3 ;
  wire \PWM_Out0_inferred__2/i__carry_n_4 ;
  wire \PWM_Out0_inferred__2/i__carry_n_5 ;
  wire \PWM_Out0_inferred__2/i__carry_n_6 ;
  wire \PWM_Out0_inferred__2/i__carry_n_7 ;
  wire [31:0]\PWM_Out_reg[0]_0 ;
  wire [31:0]\PWM_Out_reg[1]_0 ;
  wire [31:0]\PWM_Out_reg[2]_0 ;
  wire [31:0]\PWM_Out_reg[3]_0 ;
  wire [31:0]Q;
  wire clear;
  wire counter0_carry__0_i_10_n_0;
  wire counter0_carry__0_i_11_n_0;
  wire counter0_carry__0_i_12_n_0;
  wire counter0_carry__0_i_13_n_0;
  wire counter0_carry__0_i_14_n_0;
  wire counter0_carry__0_i_15_n_0;
  wire counter0_carry__0_i_16_n_0;
  wire counter0_carry__0_i_1_n_0;
  wire counter0_carry__0_i_2_n_0;
  wire counter0_carry__0_i_3_n_0;
  wire counter0_carry__0_i_4_n_0;
  wire counter0_carry__0_i_5_n_0;
  wire counter0_carry__0_i_6_n_0;
  wire counter0_carry__0_i_7_n_0;
  wire counter0_carry__0_i_8_n_0;
  wire counter0_carry__0_i_9_n_0;
  wire counter0_carry__0_n_1;
  wire counter0_carry__0_n_2;
  wire counter0_carry__0_n_3;
  wire counter0_carry__0_n_4;
  wire counter0_carry__0_n_5;
  wire counter0_carry__0_n_6;
  wire counter0_carry__0_n_7;
  wire counter0_carry_i_10_n_0;
  wire counter0_carry_i_11_n_0;
  wire counter0_carry_i_12_n_0;
  wire counter0_carry_i_13_n_0;
  wire counter0_carry_i_14_n_0;
  wire counter0_carry_i_15_n_0;
  wire counter0_carry_i_16_n_0;
  wire counter0_carry_i_1_n_0;
  wire counter0_carry_i_2_n_0;
  wire counter0_carry_i_3_n_0;
  wire counter0_carry_i_4_n_0;
  wire counter0_carry_i_5_n_0;
  wire counter0_carry_i_6_n_0;
  wire counter0_carry_i_7_n_0;
  wire counter0_carry_i_8_n_0;
  wire counter0_carry_i_9_n_0;
  wire counter0_carry_n_0;
  wire counter0_carry_n_1;
  wire counter0_carry_n_2;
  wire counter0_carry_n_3;
  wire counter0_carry_n_4;
  wire counter0_carry_n_5;
  wire counter0_carry_n_6;
  wire counter0_carry_n_7;
  wire \counter[0]_i_2_n_0 ;
  wire [31:0]counter_reg;
  wire \counter_reg[0]_i_1_n_0 ;
  wire \counter_reg[0]_i_1_n_1 ;
  wire \counter_reg[0]_i_1_n_10 ;
  wire \counter_reg[0]_i_1_n_11 ;
  wire \counter_reg[0]_i_1_n_12 ;
  wire \counter_reg[0]_i_1_n_13 ;
  wire \counter_reg[0]_i_1_n_14 ;
  wire \counter_reg[0]_i_1_n_15 ;
  wire \counter_reg[0]_i_1_n_2 ;
  wire \counter_reg[0]_i_1_n_3 ;
  wire \counter_reg[0]_i_1_n_4 ;
  wire \counter_reg[0]_i_1_n_5 ;
  wire \counter_reg[0]_i_1_n_6 ;
  wire \counter_reg[0]_i_1_n_7 ;
  wire \counter_reg[0]_i_1_n_8 ;
  wire \counter_reg[0]_i_1_n_9 ;
  wire \counter_reg[16]_i_1_n_0 ;
  wire \counter_reg[16]_i_1_n_1 ;
  wire \counter_reg[16]_i_1_n_10 ;
  wire \counter_reg[16]_i_1_n_11 ;
  wire \counter_reg[16]_i_1_n_12 ;
  wire \counter_reg[16]_i_1_n_13 ;
  wire \counter_reg[16]_i_1_n_14 ;
  wire \counter_reg[16]_i_1_n_15 ;
  wire \counter_reg[16]_i_1_n_2 ;
  wire \counter_reg[16]_i_1_n_3 ;
  wire \counter_reg[16]_i_1_n_4 ;
  wire \counter_reg[16]_i_1_n_5 ;
  wire \counter_reg[16]_i_1_n_6 ;
  wire \counter_reg[16]_i_1_n_7 ;
  wire \counter_reg[16]_i_1_n_8 ;
  wire \counter_reg[16]_i_1_n_9 ;
  wire \counter_reg[24]_i_1_n_1 ;
  wire \counter_reg[24]_i_1_n_10 ;
  wire \counter_reg[24]_i_1_n_11 ;
  wire \counter_reg[24]_i_1_n_12 ;
  wire \counter_reg[24]_i_1_n_13 ;
  wire \counter_reg[24]_i_1_n_14 ;
  wire \counter_reg[24]_i_1_n_15 ;
  wire \counter_reg[24]_i_1_n_2 ;
  wire \counter_reg[24]_i_1_n_3 ;
  wire \counter_reg[24]_i_1_n_4 ;
  wire \counter_reg[24]_i_1_n_5 ;
  wire \counter_reg[24]_i_1_n_6 ;
  wire \counter_reg[24]_i_1_n_7 ;
  wire \counter_reg[24]_i_1_n_8 ;
  wire \counter_reg[24]_i_1_n_9 ;
  wire \counter_reg[8]_i_1_n_0 ;
  wire \counter_reg[8]_i_1_n_1 ;
  wire \counter_reg[8]_i_1_n_10 ;
  wire \counter_reg[8]_i_1_n_11 ;
  wire \counter_reg[8]_i_1_n_12 ;
  wire \counter_reg[8]_i_1_n_13 ;
  wire \counter_reg[8]_i_1_n_14 ;
  wire \counter_reg[8]_i_1_n_15 ;
  wire \counter_reg[8]_i_1_n_2 ;
  wire \counter_reg[8]_i_1_n_3 ;
  wire \counter_reg[8]_i_1_n_4 ;
  wire \counter_reg[8]_i_1_n_5 ;
  wire \counter_reg[8]_i_1_n_6 ;
  wire \counter_reg[8]_i_1_n_7 ;
  wire \counter_reg[8]_i_1_n_8 ;
  wire \counter_reg[8]_i_1_n_9 ;
  wire i__carry__0_i_10__0_n_0;
  wire i__carry__0_i_10__1_n_0;
  wire i__carry__0_i_10_n_0;
  wire i__carry__0_i_11__0_n_0;
  wire i__carry__0_i_11__1_n_0;
  wire i__carry__0_i_11_n_0;
  wire i__carry__0_i_12__0_n_0;
  wire i__carry__0_i_12__1_n_0;
  wire i__carry__0_i_12_n_0;
  wire i__carry__0_i_13__0_n_0;
  wire i__carry__0_i_13__1_n_0;
  wire i__carry__0_i_13_n_0;
  wire i__carry__0_i_14__0_n_0;
  wire i__carry__0_i_14__1_n_0;
  wire i__carry__0_i_14_n_0;
  wire i__carry__0_i_15__0_n_0;
  wire i__carry__0_i_15__1_n_0;
  wire i__carry__0_i_15_n_0;
  wire i__carry__0_i_16__0_n_0;
  wire i__carry__0_i_16__1_n_0;
  wire i__carry__0_i_16_n_0;
  wire i__carry__0_i_1__0_n_0;
  wire i__carry__0_i_1__1_n_0;
  wire i__carry__0_i_1_n_0;
  wire i__carry__0_i_2__0_n_0;
  wire i__carry__0_i_2__1_n_0;
  wire i__carry__0_i_2_n_0;
  wire i__carry__0_i_3__0_n_0;
  wire i__carry__0_i_3__1_n_0;
  wire i__carry__0_i_3_n_0;
  wire i__carry__0_i_4__0_n_0;
  wire i__carry__0_i_4__1_n_0;
  wire i__carry__0_i_4_n_0;
  wire i__carry__0_i_5__0_n_0;
  wire i__carry__0_i_5__1_n_0;
  wire i__carry__0_i_5_n_0;
  wire i__carry__0_i_6__0_n_0;
  wire i__carry__0_i_6__1_n_0;
  wire i__carry__0_i_6_n_0;
  wire i__carry__0_i_7__0_n_0;
  wire i__carry__0_i_7__1_n_0;
  wire i__carry__0_i_7_n_0;
  wire i__carry__0_i_8__0_n_0;
  wire i__carry__0_i_8__1_n_0;
  wire i__carry__0_i_8_n_0;
  wire i__carry__0_i_9__0_n_0;
  wire i__carry__0_i_9__1_n_0;
  wire i__carry__0_i_9_n_0;
  wire i__carry_i_10__0_n_0;
  wire i__carry_i_10__1_n_0;
  wire i__carry_i_10_n_0;
  wire i__carry_i_11__0_n_0;
  wire i__carry_i_11__1_n_0;
  wire i__carry_i_11_n_0;
  wire i__carry_i_12__0_n_0;
  wire i__carry_i_12__1_n_0;
  wire i__carry_i_12_n_0;
  wire i__carry_i_13__0_n_0;
  wire i__carry_i_13__1_n_0;
  wire i__carry_i_13_n_0;
  wire i__carry_i_14__0_n_0;
  wire i__carry_i_14__1_n_0;
  wire i__carry_i_14_n_0;
  wire i__carry_i_15__0_n_0;
  wire i__carry_i_15__1_n_0;
  wire i__carry_i_15_n_0;
  wire i__carry_i_16__0_n_0;
  wire i__carry_i_16__1_n_0;
  wire i__carry_i_16_n_0;
  wire i__carry_i_1__0_n_0;
  wire i__carry_i_1__1_n_0;
  wire i__carry_i_1_n_0;
  wire i__carry_i_2__0_n_0;
  wire i__carry_i_2__1_n_0;
  wire i__carry_i_2_n_0;
  wire i__carry_i_3__0_n_0;
  wire i__carry_i_3__1_n_0;
  wire i__carry_i_3_n_0;
  wire i__carry_i_4__0_n_0;
  wire i__carry_i_4__1_n_0;
  wire i__carry_i_4_n_0;
  wire i__carry_i_5__0_n_0;
  wire i__carry_i_5__1_n_0;
  wire i__carry_i_5_n_0;
  wire i__carry_i_6__0_n_0;
  wire i__carry_i_6__1_n_0;
  wire i__carry_i_6_n_0;
  wire i__carry_i_7__0_n_0;
  wire i__carry_i_7__1_n_0;
  wire i__carry_i_7_n_0;
  wire i__carry_i_8__0_n_0;
  wire i__carry_i_8__1_n_0;
  wire i__carry_i_8_n_0;
  wire i__carry_i_9__0_n_0;
  wire i__carry_i_9__1_n_0;
  wire i__carry_i_9_n_0;
  wire pwm_axi_aclk;
  wire [7:0]NLW_PWM_Out0_carry_O_UNCONNECTED;
  wire [7:0]NLW_PWM_Out0_carry__0_O_UNCONNECTED;
  wire [7:0]\NLW_PWM_Out0_inferred__0/i__carry_O_UNCONNECTED ;
  wire [7:0]\NLW_PWM_Out0_inferred__0/i__carry__0_O_UNCONNECTED ;
  wire [7:0]\NLW_PWM_Out0_inferred__1/i__carry_O_UNCONNECTED ;
  wire [7:0]\NLW_PWM_Out0_inferred__1/i__carry__0_O_UNCONNECTED ;
  wire [7:0]\NLW_PWM_Out0_inferred__2/i__carry_O_UNCONNECTED ;
  wire [7:0]\NLW_PWM_Out0_inferred__2/i__carry__0_O_UNCONNECTED ;
  wire [7:0]NLW_counter0_carry_O_UNCONNECTED;
  wire [7:0]NLW_counter0_carry__0_O_UNCONNECTED;
  wire [7:7]\NLW_counter_reg[24]_i_1_CO_UNCONNECTED ;

  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY8 PWM_Out0_carry
       (.CI(1'b0),
        .CI_TOP(1'b0),
        .CO({PWM_Out0_carry_n_0,PWM_Out0_carry_n_1,PWM_Out0_carry_n_2,PWM_Out0_carry_n_3,PWM_Out0_carry_n_4,PWM_Out0_carry_n_5,PWM_Out0_carry_n_6,PWM_Out0_carry_n_7}),
        .DI({PWM_Out0_carry_i_1_n_0,PWM_Out0_carry_i_2_n_0,PWM_Out0_carry_i_3_n_0,PWM_Out0_carry_i_4_n_0,PWM_Out0_carry_i_5_n_0,PWM_Out0_carry_i_6_n_0,PWM_Out0_carry_i_7_n_0,PWM_Out0_carry_i_8_n_0}),
        .O(NLW_PWM_Out0_carry_O_UNCONNECTED[7:0]),
        .S({PWM_Out0_carry_i_9_n_0,PWM_Out0_carry_i_10_n_0,PWM_Out0_carry_i_11_n_0,PWM_Out0_carry_i_12_n_0,PWM_Out0_carry_i_13_n_0,PWM_Out0_carry_i_14_n_0,PWM_Out0_carry_i_15_n_0,PWM_Out0_carry_i_16_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY8 PWM_Out0_carry__0
       (.CI(PWM_Out0_carry_n_0),
        .CI_TOP(1'b0),
        .CO({PWM_Out0_carry__0_n_0,PWM_Out0_carry__0_n_1,PWM_Out0_carry__0_n_2,PWM_Out0_carry__0_n_3,PWM_Out0_carry__0_n_4,PWM_Out0_carry__0_n_5,PWM_Out0_carry__0_n_6,PWM_Out0_carry__0_n_7}),
        .DI({PWM_Out0_carry__0_i_1_n_0,PWM_Out0_carry__0_i_2_n_0,PWM_Out0_carry__0_i_3_n_0,PWM_Out0_carry__0_i_4_n_0,PWM_Out0_carry__0_i_5_n_0,PWM_Out0_carry__0_i_6_n_0,PWM_Out0_carry__0_i_7_n_0,PWM_Out0_carry__0_i_8_n_0}),
        .O(NLW_PWM_Out0_carry__0_O_UNCONNECTED[7:0]),
        .S({PWM_Out0_carry__0_i_9_n_0,PWM_Out0_carry__0_i_10_n_0,PWM_Out0_carry__0_i_11_n_0,PWM_Out0_carry__0_i_12_n_0,PWM_Out0_carry__0_i_13_n_0,PWM_Out0_carry__0_i_14_n_0,PWM_Out0_carry__0_i_15_n_0,PWM_Out0_carry__0_i_16_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    PWM_Out0_carry__0_i_1
       (.I0(\PWM_Out_reg[0]_0 [30]),
        .I1(counter_reg[30]),
        .I2(counter_reg[31]),
        .I3(\PWM_Out_reg[0]_0 [31]),
        .O(PWM_Out0_carry__0_i_1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    PWM_Out0_carry__0_i_10
       (.I0(\PWM_Out_reg[0]_0 [28]),
        .I1(counter_reg[28]),
        .I2(\PWM_Out_reg[0]_0 [29]),
        .I3(counter_reg[29]),
        .O(PWM_Out0_carry__0_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    PWM_Out0_carry__0_i_11
       (.I0(\PWM_Out_reg[0]_0 [26]),
        .I1(counter_reg[26]),
        .I2(\PWM_Out_reg[0]_0 [27]),
        .I3(counter_reg[27]),
        .O(PWM_Out0_carry__0_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    PWM_Out0_carry__0_i_12
       (.I0(\PWM_Out_reg[0]_0 [24]),
        .I1(counter_reg[24]),
        .I2(\PWM_Out_reg[0]_0 [25]),
        .I3(counter_reg[25]),
        .O(PWM_Out0_carry__0_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    PWM_Out0_carry__0_i_13
       (.I0(\PWM_Out_reg[0]_0 [22]),
        .I1(counter_reg[22]),
        .I2(\PWM_Out_reg[0]_0 [23]),
        .I3(counter_reg[23]),
        .O(PWM_Out0_carry__0_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    PWM_Out0_carry__0_i_14
       (.I0(\PWM_Out_reg[0]_0 [20]),
        .I1(counter_reg[20]),
        .I2(\PWM_Out_reg[0]_0 [21]),
        .I3(counter_reg[21]),
        .O(PWM_Out0_carry__0_i_14_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    PWM_Out0_carry__0_i_15
       (.I0(\PWM_Out_reg[0]_0 [18]),
        .I1(counter_reg[18]),
        .I2(\PWM_Out_reg[0]_0 [19]),
        .I3(counter_reg[19]),
        .O(PWM_Out0_carry__0_i_15_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    PWM_Out0_carry__0_i_16
       (.I0(\PWM_Out_reg[0]_0 [16]),
        .I1(counter_reg[16]),
        .I2(\PWM_Out_reg[0]_0 [17]),
        .I3(counter_reg[17]),
        .O(PWM_Out0_carry__0_i_16_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    PWM_Out0_carry__0_i_2
       (.I0(\PWM_Out_reg[0]_0 [28]),
        .I1(counter_reg[28]),
        .I2(counter_reg[29]),
        .I3(\PWM_Out_reg[0]_0 [29]),
        .O(PWM_Out0_carry__0_i_2_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    PWM_Out0_carry__0_i_3
       (.I0(\PWM_Out_reg[0]_0 [26]),
        .I1(counter_reg[26]),
        .I2(counter_reg[27]),
        .I3(\PWM_Out_reg[0]_0 [27]),
        .O(PWM_Out0_carry__0_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    PWM_Out0_carry__0_i_4
       (.I0(\PWM_Out_reg[0]_0 [24]),
        .I1(counter_reg[24]),
        .I2(counter_reg[25]),
        .I3(\PWM_Out_reg[0]_0 [25]),
        .O(PWM_Out0_carry__0_i_4_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    PWM_Out0_carry__0_i_5
       (.I0(\PWM_Out_reg[0]_0 [22]),
        .I1(counter_reg[22]),
        .I2(counter_reg[23]),
        .I3(\PWM_Out_reg[0]_0 [23]),
        .O(PWM_Out0_carry__0_i_5_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    PWM_Out0_carry__0_i_6
       (.I0(\PWM_Out_reg[0]_0 [20]),
        .I1(counter_reg[20]),
        .I2(counter_reg[21]),
        .I3(\PWM_Out_reg[0]_0 [21]),
        .O(PWM_Out0_carry__0_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    PWM_Out0_carry__0_i_7
       (.I0(\PWM_Out_reg[0]_0 [18]),
        .I1(counter_reg[18]),
        .I2(counter_reg[19]),
        .I3(\PWM_Out_reg[0]_0 [19]),
        .O(PWM_Out0_carry__0_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    PWM_Out0_carry__0_i_8
       (.I0(\PWM_Out_reg[0]_0 [16]),
        .I1(counter_reg[16]),
        .I2(counter_reg[17]),
        .I3(\PWM_Out_reg[0]_0 [17]),
        .O(PWM_Out0_carry__0_i_8_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    PWM_Out0_carry__0_i_9
       (.I0(\PWM_Out_reg[0]_0 [30]),
        .I1(counter_reg[30]),
        .I2(\PWM_Out_reg[0]_0 [31]),
        .I3(counter_reg[31]),
        .O(PWM_Out0_carry__0_i_9_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    PWM_Out0_carry_i_1
       (.I0(\PWM_Out_reg[0]_0 [14]),
        .I1(counter_reg[14]),
        .I2(counter_reg[15]),
        .I3(\PWM_Out_reg[0]_0 [15]),
        .O(PWM_Out0_carry_i_1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    PWM_Out0_carry_i_10
       (.I0(\PWM_Out_reg[0]_0 [12]),
        .I1(counter_reg[12]),
        .I2(\PWM_Out_reg[0]_0 [13]),
        .I3(counter_reg[13]),
        .O(PWM_Out0_carry_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    PWM_Out0_carry_i_11
       (.I0(\PWM_Out_reg[0]_0 [10]),
        .I1(counter_reg[10]),
        .I2(\PWM_Out_reg[0]_0 [11]),
        .I3(counter_reg[11]),
        .O(PWM_Out0_carry_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    PWM_Out0_carry_i_12
       (.I0(\PWM_Out_reg[0]_0 [8]),
        .I1(counter_reg[8]),
        .I2(\PWM_Out_reg[0]_0 [9]),
        .I3(counter_reg[9]),
        .O(PWM_Out0_carry_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    PWM_Out0_carry_i_13
       (.I0(\PWM_Out_reg[0]_0 [6]),
        .I1(counter_reg[6]),
        .I2(\PWM_Out_reg[0]_0 [7]),
        .I3(counter_reg[7]),
        .O(PWM_Out0_carry_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    PWM_Out0_carry_i_14
       (.I0(\PWM_Out_reg[0]_0 [4]),
        .I1(counter_reg[4]),
        .I2(\PWM_Out_reg[0]_0 [5]),
        .I3(counter_reg[5]),
        .O(PWM_Out0_carry_i_14_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    PWM_Out0_carry_i_15
       (.I0(\PWM_Out_reg[0]_0 [2]),
        .I1(counter_reg[2]),
        .I2(\PWM_Out_reg[0]_0 [3]),
        .I3(counter_reg[3]),
        .O(PWM_Out0_carry_i_15_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    PWM_Out0_carry_i_16
       (.I0(\PWM_Out_reg[0]_0 [0]),
        .I1(counter_reg[0]),
        .I2(\PWM_Out_reg[0]_0 [1]),
        .I3(counter_reg[1]),
        .O(PWM_Out0_carry_i_16_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    PWM_Out0_carry_i_2
       (.I0(\PWM_Out_reg[0]_0 [12]),
        .I1(counter_reg[12]),
        .I2(counter_reg[13]),
        .I3(\PWM_Out_reg[0]_0 [13]),
        .O(PWM_Out0_carry_i_2_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    PWM_Out0_carry_i_3
       (.I0(\PWM_Out_reg[0]_0 [10]),
        .I1(counter_reg[10]),
        .I2(counter_reg[11]),
        .I3(\PWM_Out_reg[0]_0 [11]),
        .O(PWM_Out0_carry_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    PWM_Out0_carry_i_4
       (.I0(\PWM_Out_reg[0]_0 [8]),
        .I1(counter_reg[8]),
        .I2(counter_reg[9]),
        .I3(\PWM_Out_reg[0]_0 [9]),
        .O(PWM_Out0_carry_i_4_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    PWM_Out0_carry_i_5
       (.I0(\PWM_Out_reg[0]_0 [6]),
        .I1(counter_reg[6]),
        .I2(counter_reg[7]),
        .I3(\PWM_Out_reg[0]_0 [7]),
        .O(PWM_Out0_carry_i_5_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    PWM_Out0_carry_i_6
       (.I0(\PWM_Out_reg[0]_0 [4]),
        .I1(counter_reg[4]),
        .I2(counter_reg[5]),
        .I3(\PWM_Out_reg[0]_0 [5]),
        .O(PWM_Out0_carry_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    PWM_Out0_carry_i_7
       (.I0(\PWM_Out_reg[0]_0 [2]),
        .I1(counter_reg[2]),
        .I2(counter_reg[3]),
        .I3(\PWM_Out_reg[0]_0 [3]),
        .O(PWM_Out0_carry_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    PWM_Out0_carry_i_8
       (.I0(\PWM_Out_reg[0]_0 [0]),
        .I1(counter_reg[0]),
        .I2(counter_reg[1]),
        .I3(\PWM_Out_reg[0]_0 [1]),
        .O(PWM_Out0_carry_i_8_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    PWM_Out0_carry_i_9
       (.I0(\PWM_Out_reg[0]_0 [14]),
        .I1(counter_reg[14]),
        .I2(\PWM_Out_reg[0]_0 [15]),
        .I3(counter_reg[15]),
        .O(PWM_Out0_carry_i_9_n_0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY8 \PWM_Out0_inferred__0/i__carry 
       (.CI(1'b0),
        .CI_TOP(1'b0),
        .CO({\PWM_Out0_inferred__0/i__carry_n_0 ,\PWM_Out0_inferred__0/i__carry_n_1 ,\PWM_Out0_inferred__0/i__carry_n_2 ,\PWM_Out0_inferred__0/i__carry_n_3 ,\PWM_Out0_inferred__0/i__carry_n_4 ,\PWM_Out0_inferred__0/i__carry_n_5 ,\PWM_Out0_inferred__0/i__carry_n_6 ,\PWM_Out0_inferred__0/i__carry_n_7 }),
        .DI({i__carry_i_1_n_0,i__carry_i_2_n_0,i__carry_i_3_n_0,i__carry_i_4_n_0,i__carry_i_5_n_0,i__carry_i_6_n_0,i__carry_i_7_n_0,i__carry_i_8_n_0}),
        .O(\NLW_PWM_Out0_inferred__0/i__carry_O_UNCONNECTED [7:0]),
        .S({i__carry_i_9_n_0,i__carry_i_10_n_0,i__carry_i_11_n_0,i__carry_i_12_n_0,i__carry_i_13_n_0,i__carry_i_14_n_0,i__carry_i_15_n_0,i__carry_i_16_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY8 \PWM_Out0_inferred__0/i__carry__0 
       (.CI(\PWM_Out0_inferred__0/i__carry_n_0 ),
        .CI_TOP(1'b0),
        .CO({\PWM_Out0_inferred__0/i__carry__0_n_0 ,\PWM_Out0_inferred__0/i__carry__0_n_1 ,\PWM_Out0_inferred__0/i__carry__0_n_2 ,\PWM_Out0_inferred__0/i__carry__0_n_3 ,\PWM_Out0_inferred__0/i__carry__0_n_4 ,\PWM_Out0_inferred__0/i__carry__0_n_5 ,\PWM_Out0_inferred__0/i__carry__0_n_6 ,\PWM_Out0_inferred__0/i__carry__0_n_7 }),
        .DI({i__carry__0_i_1_n_0,i__carry__0_i_2_n_0,i__carry__0_i_3_n_0,i__carry__0_i_4_n_0,i__carry__0_i_5_n_0,i__carry__0_i_6_n_0,i__carry__0_i_7_n_0,i__carry__0_i_8_n_0}),
        .O(\NLW_PWM_Out0_inferred__0/i__carry__0_O_UNCONNECTED [7:0]),
        .S({i__carry__0_i_9_n_0,i__carry__0_i_10_n_0,i__carry__0_i_11_n_0,i__carry__0_i_12_n_0,i__carry__0_i_13_n_0,i__carry__0_i_14_n_0,i__carry__0_i_15_n_0,i__carry__0_i_16_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY8 \PWM_Out0_inferred__1/i__carry 
       (.CI(1'b0),
        .CI_TOP(1'b0),
        .CO({\PWM_Out0_inferred__1/i__carry_n_0 ,\PWM_Out0_inferred__1/i__carry_n_1 ,\PWM_Out0_inferred__1/i__carry_n_2 ,\PWM_Out0_inferred__1/i__carry_n_3 ,\PWM_Out0_inferred__1/i__carry_n_4 ,\PWM_Out0_inferred__1/i__carry_n_5 ,\PWM_Out0_inferred__1/i__carry_n_6 ,\PWM_Out0_inferred__1/i__carry_n_7 }),
        .DI({i__carry_i_1__0_n_0,i__carry_i_2__0_n_0,i__carry_i_3__0_n_0,i__carry_i_4__0_n_0,i__carry_i_5__0_n_0,i__carry_i_6__0_n_0,i__carry_i_7__0_n_0,i__carry_i_8__0_n_0}),
        .O(\NLW_PWM_Out0_inferred__1/i__carry_O_UNCONNECTED [7:0]),
        .S({i__carry_i_9__0_n_0,i__carry_i_10__0_n_0,i__carry_i_11__0_n_0,i__carry_i_12__0_n_0,i__carry_i_13__0_n_0,i__carry_i_14__0_n_0,i__carry_i_15__0_n_0,i__carry_i_16__0_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY8 \PWM_Out0_inferred__1/i__carry__0 
       (.CI(\PWM_Out0_inferred__1/i__carry_n_0 ),
        .CI_TOP(1'b0),
        .CO({\PWM_Out0_inferred__1/i__carry__0_n_0 ,\PWM_Out0_inferred__1/i__carry__0_n_1 ,\PWM_Out0_inferred__1/i__carry__0_n_2 ,\PWM_Out0_inferred__1/i__carry__0_n_3 ,\PWM_Out0_inferred__1/i__carry__0_n_4 ,\PWM_Out0_inferred__1/i__carry__0_n_5 ,\PWM_Out0_inferred__1/i__carry__0_n_6 ,\PWM_Out0_inferred__1/i__carry__0_n_7 }),
        .DI({i__carry__0_i_1__0_n_0,i__carry__0_i_2__0_n_0,i__carry__0_i_3__0_n_0,i__carry__0_i_4__0_n_0,i__carry__0_i_5__0_n_0,i__carry__0_i_6__0_n_0,i__carry__0_i_7__0_n_0,i__carry__0_i_8__0_n_0}),
        .O(\NLW_PWM_Out0_inferred__1/i__carry__0_O_UNCONNECTED [7:0]),
        .S({i__carry__0_i_9__0_n_0,i__carry__0_i_10__0_n_0,i__carry__0_i_11__0_n_0,i__carry__0_i_12__0_n_0,i__carry__0_i_13__0_n_0,i__carry__0_i_14__0_n_0,i__carry__0_i_15__0_n_0,i__carry__0_i_16__0_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY8 \PWM_Out0_inferred__2/i__carry 
       (.CI(1'b0),
        .CI_TOP(1'b0),
        .CO({\PWM_Out0_inferred__2/i__carry_n_0 ,\PWM_Out0_inferred__2/i__carry_n_1 ,\PWM_Out0_inferred__2/i__carry_n_2 ,\PWM_Out0_inferred__2/i__carry_n_3 ,\PWM_Out0_inferred__2/i__carry_n_4 ,\PWM_Out0_inferred__2/i__carry_n_5 ,\PWM_Out0_inferred__2/i__carry_n_6 ,\PWM_Out0_inferred__2/i__carry_n_7 }),
        .DI({i__carry_i_1__1_n_0,i__carry_i_2__1_n_0,i__carry_i_3__1_n_0,i__carry_i_4__1_n_0,i__carry_i_5__1_n_0,i__carry_i_6__1_n_0,i__carry_i_7__1_n_0,i__carry_i_8__1_n_0}),
        .O(\NLW_PWM_Out0_inferred__2/i__carry_O_UNCONNECTED [7:0]),
        .S({i__carry_i_9__1_n_0,i__carry_i_10__1_n_0,i__carry_i_11__1_n_0,i__carry_i_12__1_n_0,i__carry_i_13__1_n_0,i__carry_i_14__1_n_0,i__carry_i_15__1_n_0,i__carry_i_16__1_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY8 \PWM_Out0_inferred__2/i__carry__0 
       (.CI(\PWM_Out0_inferred__2/i__carry_n_0 ),
        .CI_TOP(1'b0),
        .CO({PWM_Out0,\PWM_Out0_inferred__2/i__carry__0_n_1 ,\PWM_Out0_inferred__2/i__carry__0_n_2 ,\PWM_Out0_inferred__2/i__carry__0_n_3 ,\PWM_Out0_inferred__2/i__carry__0_n_4 ,\PWM_Out0_inferred__2/i__carry__0_n_5 ,\PWM_Out0_inferred__2/i__carry__0_n_6 ,\PWM_Out0_inferred__2/i__carry__0_n_7 }),
        .DI({i__carry__0_i_1__1_n_0,i__carry__0_i_2__1_n_0,i__carry__0_i_3__1_n_0,i__carry__0_i_4__1_n_0,i__carry__0_i_5__1_n_0,i__carry__0_i_6__1_n_0,i__carry__0_i_7__1_n_0,i__carry__0_i_8__1_n_0}),
        .O(\NLW_PWM_Out0_inferred__2/i__carry__0_O_UNCONNECTED [7:0]),
        .S({i__carry__0_i_9__1_n_0,i__carry__0_i_10__1_n_0,i__carry__0_i_11__1_n_0,i__carry__0_i_12__1_n_0,i__carry__0_i_13__1_n_0,i__carry__0_i_14__1_n_0,i__carry__0_i_15__1_n_0,i__carry__0_i_16__1_n_0}));
  FDRE \PWM_Out_reg[0] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(PWM_Out0_carry__0_n_0),
        .Q(PWM_Out[0]),
        .R(1'b0));
  FDRE \PWM_Out_reg[1] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\PWM_Out0_inferred__0/i__carry__0_n_0 ),
        .Q(PWM_Out[1]),
        .R(1'b0));
  FDRE \PWM_Out_reg[2] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\PWM_Out0_inferred__1/i__carry__0_n_0 ),
        .Q(PWM_Out[2]),
        .R(1'b0));
  FDRE \PWM_Out_reg[3] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(PWM_Out0),
        .Q(PWM_Out[3]),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "14" *) 
  CARRY8 counter0_carry
       (.CI(1'b0),
        .CI_TOP(1'b0),
        .CO({counter0_carry_n_0,counter0_carry_n_1,counter0_carry_n_2,counter0_carry_n_3,counter0_carry_n_4,counter0_carry_n_5,counter0_carry_n_6,counter0_carry_n_7}),
        .DI({counter0_carry_i_1_n_0,counter0_carry_i_2_n_0,counter0_carry_i_3_n_0,counter0_carry_i_4_n_0,counter0_carry_i_5_n_0,counter0_carry_i_6_n_0,counter0_carry_i_7_n_0,counter0_carry_i_8_n_0}),
        .O(NLW_counter0_carry_O_UNCONNECTED[7:0]),
        .S({counter0_carry_i_9_n_0,counter0_carry_i_10_n_0,counter0_carry_i_11_n_0,counter0_carry_i_12_n_0,counter0_carry_i_13_n_0,counter0_carry_i_14_n_0,counter0_carry_i_15_n_0,counter0_carry_i_16_n_0}));
  (* COMPARATOR_THRESHOLD = "14" *) 
  CARRY8 counter0_carry__0
       (.CI(counter0_carry_n_0),
        .CI_TOP(1'b0),
        .CO({clear,counter0_carry__0_n_1,counter0_carry__0_n_2,counter0_carry__0_n_3,counter0_carry__0_n_4,counter0_carry__0_n_5,counter0_carry__0_n_6,counter0_carry__0_n_7}),
        .DI({counter0_carry__0_i_1_n_0,counter0_carry__0_i_2_n_0,counter0_carry__0_i_3_n_0,counter0_carry__0_i_4_n_0,counter0_carry__0_i_5_n_0,counter0_carry__0_i_6_n_0,counter0_carry__0_i_7_n_0,counter0_carry__0_i_8_n_0}),
        .O(NLW_counter0_carry__0_O_UNCONNECTED[7:0]),
        .S({counter0_carry__0_i_9_n_0,counter0_carry__0_i_10_n_0,counter0_carry__0_i_11_n_0,counter0_carry__0_i_12_n_0,counter0_carry__0_i_13_n_0,counter0_carry__0_i_14_n_0,counter0_carry__0_i_15_n_0,counter0_carry__0_i_16_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    counter0_carry__0_i_1
       (.I0(counter_reg[30]),
        .I1(Q[30]),
        .I2(Q[31]),
        .I3(counter_reg[31]),
        .O(counter0_carry__0_i_1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    counter0_carry__0_i_10
       (.I0(counter_reg[28]),
        .I1(Q[28]),
        .I2(counter_reg[29]),
        .I3(Q[29]),
        .O(counter0_carry__0_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    counter0_carry__0_i_11
       (.I0(counter_reg[26]),
        .I1(Q[26]),
        .I2(counter_reg[27]),
        .I3(Q[27]),
        .O(counter0_carry__0_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    counter0_carry__0_i_12
       (.I0(counter_reg[24]),
        .I1(Q[24]),
        .I2(counter_reg[25]),
        .I3(Q[25]),
        .O(counter0_carry__0_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    counter0_carry__0_i_13
       (.I0(counter_reg[22]),
        .I1(Q[22]),
        .I2(counter_reg[23]),
        .I3(Q[23]),
        .O(counter0_carry__0_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    counter0_carry__0_i_14
       (.I0(counter_reg[20]),
        .I1(Q[20]),
        .I2(counter_reg[21]),
        .I3(Q[21]),
        .O(counter0_carry__0_i_14_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    counter0_carry__0_i_15
       (.I0(counter_reg[18]),
        .I1(Q[18]),
        .I2(counter_reg[19]),
        .I3(Q[19]),
        .O(counter0_carry__0_i_15_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    counter0_carry__0_i_16
       (.I0(counter_reg[16]),
        .I1(Q[16]),
        .I2(counter_reg[17]),
        .I3(Q[17]),
        .O(counter0_carry__0_i_16_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    counter0_carry__0_i_2
       (.I0(counter_reg[28]),
        .I1(Q[28]),
        .I2(Q[29]),
        .I3(counter_reg[29]),
        .O(counter0_carry__0_i_2_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    counter0_carry__0_i_3
       (.I0(counter_reg[26]),
        .I1(Q[26]),
        .I2(Q[27]),
        .I3(counter_reg[27]),
        .O(counter0_carry__0_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    counter0_carry__0_i_4
       (.I0(counter_reg[24]),
        .I1(Q[24]),
        .I2(Q[25]),
        .I3(counter_reg[25]),
        .O(counter0_carry__0_i_4_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    counter0_carry__0_i_5
       (.I0(counter_reg[22]),
        .I1(Q[22]),
        .I2(Q[23]),
        .I3(counter_reg[23]),
        .O(counter0_carry__0_i_5_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    counter0_carry__0_i_6
       (.I0(counter_reg[20]),
        .I1(Q[20]),
        .I2(Q[21]),
        .I3(counter_reg[21]),
        .O(counter0_carry__0_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    counter0_carry__0_i_7
       (.I0(counter_reg[18]),
        .I1(Q[18]),
        .I2(Q[19]),
        .I3(counter_reg[19]),
        .O(counter0_carry__0_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    counter0_carry__0_i_8
       (.I0(counter_reg[16]),
        .I1(Q[16]),
        .I2(Q[17]),
        .I3(counter_reg[17]),
        .O(counter0_carry__0_i_8_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    counter0_carry__0_i_9
       (.I0(counter_reg[30]),
        .I1(Q[30]),
        .I2(counter_reg[31]),
        .I3(Q[31]),
        .O(counter0_carry__0_i_9_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    counter0_carry_i_1
       (.I0(counter_reg[14]),
        .I1(Q[14]),
        .I2(Q[15]),
        .I3(counter_reg[15]),
        .O(counter0_carry_i_1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    counter0_carry_i_10
       (.I0(counter_reg[12]),
        .I1(Q[12]),
        .I2(counter_reg[13]),
        .I3(Q[13]),
        .O(counter0_carry_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    counter0_carry_i_11
       (.I0(counter_reg[10]),
        .I1(Q[10]),
        .I2(counter_reg[11]),
        .I3(Q[11]),
        .O(counter0_carry_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    counter0_carry_i_12
       (.I0(counter_reg[8]),
        .I1(Q[8]),
        .I2(counter_reg[9]),
        .I3(Q[9]),
        .O(counter0_carry_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    counter0_carry_i_13
       (.I0(counter_reg[6]),
        .I1(Q[6]),
        .I2(counter_reg[7]),
        .I3(Q[7]),
        .O(counter0_carry_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    counter0_carry_i_14
       (.I0(counter_reg[4]),
        .I1(Q[4]),
        .I2(counter_reg[5]),
        .I3(Q[5]),
        .O(counter0_carry_i_14_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    counter0_carry_i_15
       (.I0(counter_reg[2]),
        .I1(Q[2]),
        .I2(counter_reg[3]),
        .I3(Q[3]),
        .O(counter0_carry_i_15_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    counter0_carry_i_16
       (.I0(counter_reg[0]),
        .I1(Q[0]),
        .I2(counter_reg[1]),
        .I3(Q[1]),
        .O(counter0_carry_i_16_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    counter0_carry_i_2
       (.I0(counter_reg[12]),
        .I1(Q[12]),
        .I2(Q[13]),
        .I3(counter_reg[13]),
        .O(counter0_carry_i_2_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    counter0_carry_i_3
       (.I0(counter_reg[10]),
        .I1(Q[10]),
        .I2(Q[11]),
        .I3(counter_reg[11]),
        .O(counter0_carry_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    counter0_carry_i_4
       (.I0(counter_reg[8]),
        .I1(Q[8]),
        .I2(Q[9]),
        .I3(counter_reg[9]),
        .O(counter0_carry_i_4_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    counter0_carry_i_5
       (.I0(counter_reg[6]),
        .I1(Q[6]),
        .I2(Q[7]),
        .I3(counter_reg[7]),
        .O(counter0_carry_i_5_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    counter0_carry_i_6
       (.I0(counter_reg[4]),
        .I1(Q[4]),
        .I2(Q[5]),
        .I3(counter_reg[5]),
        .O(counter0_carry_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    counter0_carry_i_7
       (.I0(counter_reg[2]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(counter_reg[3]),
        .O(counter0_carry_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    counter0_carry_i_8
       (.I0(counter_reg[0]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(counter_reg[1]),
        .O(counter0_carry_i_8_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    counter0_carry_i_9
       (.I0(counter_reg[14]),
        .I1(Q[14]),
        .I2(counter_reg[15]),
        .I3(Q[15]),
        .O(counter0_carry_i_9_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    \counter[0]_i_2 
       (.I0(counter_reg[0]),
        .O(\counter[0]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[0] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[0]_i_1_n_15 ),
        .Q(counter_reg[0]),
        .R(clear));
  (* ADDER_THRESHOLD = "16" *) 
  CARRY8 \counter_reg[0]_i_1 
       (.CI(1'b0),
        .CI_TOP(1'b0),
        .CO({\counter_reg[0]_i_1_n_0 ,\counter_reg[0]_i_1_n_1 ,\counter_reg[0]_i_1_n_2 ,\counter_reg[0]_i_1_n_3 ,\counter_reg[0]_i_1_n_4 ,\counter_reg[0]_i_1_n_5 ,\counter_reg[0]_i_1_n_6 ,\counter_reg[0]_i_1_n_7 }),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
        .O({\counter_reg[0]_i_1_n_8 ,\counter_reg[0]_i_1_n_9 ,\counter_reg[0]_i_1_n_10 ,\counter_reg[0]_i_1_n_11 ,\counter_reg[0]_i_1_n_12 ,\counter_reg[0]_i_1_n_13 ,\counter_reg[0]_i_1_n_14 ,\counter_reg[0]_i_1_n_15 }),
        .S({counter_reg[7:1],\counter[0]_i_2_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[10] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[8]_i_1_n_13 ),
        .Q(counter_reg[10]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[11] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[8]_i_1_n_12 ),
        .Q(counter_reg[11]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[12] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[8]_i_1_n_11 ),
        .Q(counter_reg[12]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[13] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[8]_i_1_n_10 ),
        .Q(counter_reg[13]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[14] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[8]_i_1_n_9 ),
        .Q(counter_reg[14]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[15] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[8]_i_1_n_8 ),
        .Q(counter_reg[15]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[16] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[16]_i_1_n_15 ),
        .Q(counter_reg[16]),
        .R(clear));
  (* ADDER_THRESHOLD = "16" *) 
  CARRY8 \counter_reg[16]_i_1 
       (.CI(\counter_reg[8]_i_1_n_0 ),
        .CI_TOP(1'b0),
        .CO({\counter_reg[16]_i_1_n_0 ,\counter_reg[16]_i_1_n_1 ,\counter_reg[16]_i_1_n_2 ,\counter_reg[16]_i_1_n_3 ,\counter_reg[16]_i_1_n_4 ,\counter_reg[16]_i_1_n_5 ,\counter_reg[16]_i_1_n_6 ,\counter_reg[16]_i_1_n_7 }),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({\counter_reg[16]_i_1_n_8 ,\counter_reg[16]_i_1_n_9 ,\counter_reg[16]_i_1_n_10 ,\counter_reg[16]_i_1_n_11 ,\counter_reg[16]_i_1_n_12 ,\counter_reg[16]_i_1_n_13 ,\counter_reg[16]_i_1_n_14 ,\counter_reg[16]_i_1_n_15 }),
        .S(counter_reg[23:16]));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[17] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[16]_i_1_n_14 ),
        .Q(counter_reg[17]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[18] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[16]_i_1_n_13 ),
        .Q(counter_reg[18]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[19] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[16]_i_1_n_12 ),
        .Q(counter_reg[19]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[1] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[0]_i_1_n_14 ),
        .Q(counter_reg[1]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[20] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[16]_i_1_n_11 ),
        .Q(counter_reg[20]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[21] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[16]_i_1_n_10 ),
        .Q(counter_reg[21]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[22] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[16]_i_1_n_9 ),
        .Q(counter_reg[22]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[23] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[16]_i_1_n_8 ),
        .Q(counter_reg[23]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[24] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[24]_i_1_n_15 ),
        .Q(counter_reg[24]),
        .R(clear));
  (* ADDER_THRESHOLD = "16" *) 
  CARRY8 \counter_reg[24]_i_1 
       (.CI(\counter_reg[16]_i_1_n_0 ),
        .CI_TOP(1'b0),
        .CO({\NLW_counter_reg[24]_i_1_CO_UNCONNECTED [7],\counter_reg[24]_i_1_n_1 ,\counter_reg[24]_i_1_n_2 ,\counter_reg[24]_i_1_n_3 ,\counter_reg[24]_i_1_n_4 ,\counter_reg[24]_i_1_n_5 ,\counter_reg[24]_i_1_n_6 ,\counter_reg[24]_i_1_n_7 }),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({\counter_reg[24]_i_1_n_8 ,\counter_reg[24]_i_1_n_9 ,\counter_reg[24]_i_1_n_10 ,\counter_reg[24]_i_1_n_11 ,\counter_reg[24]_i_1_n_12 ,\counter_reg[24]_i_1_n_13 ,\counter_reg[24]_i_1_n_14 ,\counter_reg[24]_i_1_n_15 }),
        .S(counter_reg[31:24]));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[25] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[24]_i_1_n_14 ),
        .Q(counter_reg[25]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[26] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[24]_i_1_n_13 ),
        .Q(counter_reg[26]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[27] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[24]_i_1_n_12 ),
        .Q(counter_reg[27]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[28] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[24]_i_1_n_11 ),
        .Q(counter_reg[28]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[29] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[24]_i_1_n_10 ),
        .Q(counter_reg[29]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[2] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[0]_i_1_n_13 ),
        .Q(counter_reg[2]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[30] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[24]_i_1_n_9 ),
        .Q(counter_reg[30]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[31] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[24]_i_1_n_8 ),
        .Q(counter_reg[31]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[3] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[0]_i_1_n_12 ),
        .Q(counter_reg[3]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[4] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[0]_i_1_n_11 ),
        .Q(counter_reg[4]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[5] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[0]_i_1_n_10 ),
        .Q(counter_reg[5]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[6] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[0]_i_1_n_9 ),
        .Q(counter_reg[6]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[7] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[0]_i_1_n_8 ),
        .Q(counter_reg[7]),
        .R(clear));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[8] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[8]_i_1_n_15 ),
        .Q(counter_reg[8]),
        .R(clear));
  (* ADDER_THRESHOLD = "16" *) 
  CARRY8 \counter_reg[8]_i_1 
       (.CI(\counter_reg[0]_i_1_n_0 ),
        .CI_TOP(1'b0),
        .CO({\counter_reg[8]_i_1_n_0 ,\counter_reg[8]_i_1_n_1 ,\counter_reg[8]_i_1_n_2 ,\counter_reg[8]_i_1_n_3 ,\counter_reg[8]_i_1_n_4 ,\counter_reg[8]_i_1_n_5 ,\counter_reg[8]_i_1_n_6 ,\counter_reg[8]_i_1_n_7 }),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({\counter_reg[8]_i_1_n_8 ,\counter_reg[8]_i_1_n_9 ,\counter_reg[8]_i_1_n_10 ,\counter_reg[8]_i_1_n_11 ,\counter_reg[8]_i_1_n_12 ,\counter_reg[8]_i_1_n_13 ,\counter_reg[8]_i_1_n_14 ,\counter_reg[8]_i_1_n_15 }),
        .S(counter_reg[15:8]));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[9] 
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(\counter_reg[8]_i_1_n_14 ),
        .Q(counter_reg[9]),
        .R(clear));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_1
       (.I0(\PWM_Out_reg[1]_0 [30]),
        .I1(counter_reg[30]),
        .I2(counter_reg[31]),
        .I3(\PWM_Out_reg[1]_0 [31]),
        .O(i__carry__0_i_1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_10
       (.I0(\PWM_Out_reg[1]_0 [28]),
        .I1(counter_reg[28]),
        .I2(\PWM_Out_reg[1]_0 [29]),
        .I3(counter_reg[29]),
        .O(i__carry__0_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_10__0
       (.I0(\PWM_Out_reg[2]_0 [28]),
        .I1(counter_reg[28]),
        .I2(\PWM_Out_reg[2]_0 [29]),
        .I3(counter_reg[29]),
        .O(i__carry__0_i_10__0_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_10__1
       (.I0(\PWM_Out_reg[3]_0 [28]),
        .I1(counter_reg[28]),
        .I2(\PWM_Out_reg[3]_0 [29]),
        .I3(counter_reg[29]),
        .O(i__carry__0_i_10__1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_11
       (.I0(\PWM_Out_reg[1]_0 [26]),
        .I1(counter_reg[26]),
        .I2(\PWM_Out_reg[1]_0 [27]),
        .I3(counter_reg[27]),
        .O(i__carry__0_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_11__0
       (.I0(\PWM_Out_reg[2]_0 [26]),
        .I1(counter_reg[26]),
        .I2(\PWM_Out_reg[2]_0 [27]),
        .I3(counter_reg[27]),
        .O(i__carry__0_i_11__0_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_11__1
       (.I0(\PWM_Out_reg[3]_0 [26]),
        .I1(counter_reg[26]),
        .I2(\PWM_Out_reg[3]_0 [27]),
        .I3(counter_reg[27]),
        .O(i__carry__0_i_11__1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_12
       (.I0(\PWM_Out_reg[1]_0 [24]),
        .I1(counter_reg[24]),
        .I2(\PWM_Out_reg[1]_0 [25]),
        .I3(counter_reg[25]),
        .O(i__carry__0_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_12__0
       (.I0(\PWM_Out_reg[2]_0 [24]),
        .I1(counter_reg[24]),
        .I2(\PWM_Out_reg[2]_0 [25]),
        .I3(counter_reg[25]),
        .O(i__carry__0_i_12__0_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_12__1
       (.I0(\PWM_Out_reg[3]_0 [24]),
        .I1(counter_reg[24]),
        .I2(\PWM_Out_reg[3]_0 [25]),
        .I3(counter_reg[25]),
        .O(i__carry__0_i_12__1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_13
       (.I0(\PWM_Out_reg[1]_0 [22]),
        .I1(counter_reg[22]),
        .I2(\PWM_Out_reg[1]_0 [23]),
        .I3(counter_reg[23]),
        .O(i__carry__0_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_13__0
       (.I0(\PWM_Out_reg[2]_0 [22]),
        .I1(counter_reg[22]),
        .I2(\PWM_Out_reg[2]_0 [23]),
        .I3(counter_reg[23]),
        .O(i__carry__0_i_13__0_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_13__1
       (.I0(\PWM_Out_reg[3]_0 [22]),
        .I1(counter_reg[22]),
        .I2(\PWM_Out_reg[3]_0 [23]),
        .I3(counter_reg[23]),
        .O(i__carry__0_i_13__1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_14
       (.I0(\PWM_Out_reg[1]_0 [20]),
        .I1(counter_reg[20]),
        .I2(\PWM_Out_reg[1]_0 [21]),
        .I3(counter_reg[21]),
        .O(i__carry__0_i_14_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_14__0
       (.I0(\PWM_Out_reg[2]_0 [20]),
        .I1(counter_reg[20]),
        .I2(\PWM_Out_reg[2]_0 [21]),
        .I3(counter_reg[21]),
        .O(i__carry__0_i_14__0_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_14__1
       (.I0(\PWM_Out_reg[3]_0 [20]),
        .I1(counter_reg[20]),
        .I2(\PWM_Out_reg[3]_0 [21]),
        .I3(counter_reg[21]),
        .O(i__carry__0_i_14__1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_15
       (.I0(\PWM_Out_reg[1]_0 [18]),
        .I1(counter_reg[18]),
        .I2(\PWM_Out_reg[1]_0 [19]),
        .I3(counter_reg[19]),
        .O(i__carry__0_i_15_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_15__0
       (.I0(\PWM_Out_reg[2]_0 [18]),
        .I1(counter_reg[18]),
        .I2(\PWM_Out_reg[2]_0 [19]),
        .I3(counter_reg[19]),
        .O(i__carry__0_i_15__0_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_15__1
       (.I0(\PWM_Out_reg[3]_0 [18]),
        .I1(counter_reg[18]),
        .I2(\PWM_Out_reg[3]_0 [19]),
        .I3(counter_reg[19]),
        .O(i__carry__0_i_15__1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_16
       (.I0(\PWM_Out_reg[1]_0 [16]),
        .I1(counter_reg[16]),
        .I2(\PWM_Out_reg[1]_0 [17]),
        .I3(counter_reg[17]),
        .O(i__carry__0_i_16_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_16__0
       (.I0(\PWM_Out_reg[2]_0 [16]),
        .I1(counter_reg[16]),
        .I2(\PWM_Out_reg[2]_0 [17]),
        .I3(counter_reg[17]),
        .O(i__carry__0_i_16__0_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_16__1
       (.I0(\PWM_Out_reg[3]_0 [16]),
        .I1(counter_reg[16]),
        .I2(\PWM_Out_reg[3]_0 [17]),
        .I3(counter_reg[17]),
        .O(i__carry__0_i_16__1_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_1__0
       (.I0(\PWM_Out_reg[2]_0 [30]),
        .I1(counter_reg[30]),
        .I2(counter_reg[31]),
        .I3(\PWM_Out_reg[2]_0 [31]),
        .O(i__carry__0_i_1__0_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_1__1
       (.I0(\PWM_Out_reg[3]_0 [30]),
        .I1(counter_reg[30]),
        .I2(counter_reg[31]),
        .I3(\PWM_Out_reg[3]_0 [31]),
        .O(i__carry__0_i_1__1_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_2
       (.I0(\PWM_Out_reg[1]_0 [28]),
        .I1(counter_reg[28]),
        .I2(counter_reg[29]),
        .I3(\PWM_Out_reg[1]_0 [29]),
        .O(i__carry__0_i_2_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_2__0
       (.I0(\PWM_Out_reg[2]_0 [28]),
        .I1(counter_reg[28]),
        .I2(counter_reg[29]),
        .I3(\PWM_Out_reg[2]_0 [29]),
        .O(i__carry__0_i_2__0_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_2__1
       (.I0(\PWM_Out_reg[3]_0 [28]),
        .I1(counter_reg[28]),
        .I2(counter_reg[29]),
        .I3(\PWM_Out_reg[3]_0 [29]),
        .O(i__carry__0_i_2__1_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_3
       (.I0(\PWM_Out_reg[1]_0 [26]),
        .I1(counter_reg[26]),
        .I2(counter_reg[27]),
        .I3(\PWM_Out_reg[1]_0 [27]),
        .O(i__carry__0_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_3__0
       (.I0(\PWM_Out_reg[2]_0 [26]),
        .I1(counter_reg[26]),
        .I2(counter_reg[27]),
        .I3(\PWM_Out_reg[2]_0 [27]),
        .O(i__carry__0_i_3__0_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_3__1
       (.I0(\PWM_Out_reg[3]_0 [26]),
        .I1(counter_reg[26]),
        .I2(counter_reg[27]),
        .I3(\PWM_Out_reg[3]_0 [27]),
        .O(i__carry__0_i_3__1_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_4
       (.I0(\PWM_Out_reg[1]_0 [24]),
        .I1(counter_reg[24]),
        .I2(counter_reg[25]),
        .I3(\PWM_Out_reg[1]_0 [25]),
        .O(i__carry__0_i_4_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_4__0
       (.I0(\PWM_Out_reg[2]_0 [24]),
        .I1(counter_reg[24]),
        .I2(counter_reg[25]),
        .I3(\PWM_Out_reg[2]_0 [25]),
        .O(i__carry__0_i_4__0_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_4__1
       (.I0(\PWM_Out_reg[3]_0 [24]),
        .I1(counter_reg[24]),
        .I2(counter_reg[25]),
        .I3(\PWM_Out_reg[3]_0 [25]),
        .O(i__carry__0_i_4__1_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_5
       (.I0(\PWM_Out_reg[1]_0 [22]),
        .I1(counter_reg[22]),
        .I2(counter_reg[23]),
        .I3(\PWM_Out_reg[1]_0 [23]),
        .O(i__carry__0_i_5_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_5__0
       (.I0(\PWM_Out_reg[2]_0 [22]),
        .I1(counter_reg[22]),
        .I2(counter_reg[23]),
        .I3(\PWM_Out_reg[2]_0 [23]),
        .O(i__carry__0_i_5__0_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_5__1
       (.I0(\PWM_Out_reg[3]_0 [22]),
        .I1(counter_reg[22]),
        .I2(counter_reg[23]),
        .I3(\PWM_Out_reg[3]_0 [23]),
        .O(i__carry__0_i_5__1_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_6
       (.I0(\PWM_Out_reg[1]_0 [20]),
        .I1(counter_reg[20]),
        .I2(counter_reg[21]),
        .I3(\PWM_Out_reg[1]_0 [21]),
        .O(i__carry__0_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_6__0
       (.I0(\PWM_Out_reg[2]_0 [20]),
        .I1(counter_reg[20]),
        .I2(counter_reg[21]),
        .I3(\PWM_Out_reg[2]_0 [21]),
        .O(i__carry__0_i_6__0_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_6__1
       (.I0(\PWM_Out_reg[3]_0 [20]),
        .I1(counter_reg[20]),
        .I2(counter_reg[21]),
        .I3(\PWM_Out_reg[3]_0 [21]),
        .O(i__carry__0_i_6__1_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_7
       (.I0(\PWM_Out_reg[1]_0 [18]),
        .I1(counter_reg[18]),
        .I2(counter_reg[19]),
        .I3(\PWM_Out_reg[1]_0 [19]),
        .O(i__carry__0_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_7__0
       (.I0(\PWM_Out_reg[2]_0 [18]),
        .I1(counter_reg[18]),
        .I2(counter_reg[19]),
        .I3(\PWM_Out_reg[2]_0 [19]),
        .O(i__carry__0_i_7__0_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_7__1
       (.I0(\PWM_Out_reg[3]_0 [18]),
        .I1(counter_reg[18]),
        .I2(counter_reg[19]),
        .I3(\PWM_Out_reg[3]_0 [19]),
        .O(i__carry__0_i_7__1_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_8
       (.I0(\PWM_Out_reg[1]_0 [16]),
        .I1(counter_reg[16]),
        .I2(counter_reg[17]),
        .I3(\PWM_Out_reg[1]_0 [17]),
        .O(i__carry__0_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_8__0
       (.I0(\PWM_Out_reg[2]_0 [16]),
        .I1(counter_reg[16]),
        .I2(counter_reg[17]),
        .I3(\PWM_Out_reg[2]_0 [17]),
        .O(i__carry__0_i_8__0_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry__0_i_8__1
       (.I0(\PWM_Out_reg[3]_0 [16]),
        .I1(counter_reg[16]),
        .I2(counter_reg[17]),
        .I3(\PWM_Out_reg[3]_0 [17]),
        .O(i__carry__0_i_8__1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_9
       (.I0(\PWM_Out_reg[1]_0 [30]),
        .I1(counter_reg[30]),
        .I2(\PWM_Out_reg[1]_0 [31]),
        .I3(counter_reg[31]),
        .O(i__carry__0_i_9_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_9__0
       (.I0(\PWM_Out_reg[2]_0 [30]),
        .I1(counter_reg[30]),
        .I2(\PWM_Out_reg[2]_0 [31]),
        .I3(counter_reg[31]),
        .O(i__carry__0_i_9__0_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry__0_i_9__1
       (.I0(\PWM_Out_reg[3]_0 [30]),
        .I1(counter_reg[30]),
        .I2(\PWM_Out_reg[3]_0 [31]),
        .I3(counter_reg[31]),
        .O(i__carry__0_i_9__1_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_1
       (.I0(\PWM_Out_reg[1]_0 [14]),
        .I1(counter_reg[14]),
        .I2(counter_reg[15]),
        .I3(\PWM_Out_reg[1]_0 [15]),
        .O(i__carry_i_1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_10
       (.I0(\PWM_Out_reg[1]_0 [12]),
        .I1(counter_reg[12]),
        .I2(\PWM_Out_reg[1]_0 [13]),
        .I3(counter_reg[13]),
        .O(i__carry_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_10__0
       (.I0(\PWM_Out_reg[2]_0 [12]),
        .I1(counter_reg[12]),
        .I2(\PWM_Out_reg[2]_0 [13]),
        .I3(counter_reg[13]),
        .O(i__carry_i_10__0_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_10__1
       (.I0(\PWM_Out_reg[3]_0 [12]),
        .I1(counter_reg[12]),
        .I2(\PWM_Out_reg[3]_0 [13]),
        .I3(counter_reg[13]),
        .O(i__carry_i_10__1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_11
       (.I0(\PWM_Out_reg[1]_0 [10]),
        .I1(counter_reg[10]),
        .I2(\PWM_Out_reg[1]_0 [11]),
        .I3(counter_reg[11]),
        .O(i__carry_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_11__0
       (.I0(\PWM_Out_reg[2]_0 [10]),
        .I1(counter_reg[10]),
        .I2(\PWM_Out_reg[2]_0 [11]),
        .I3(counter_reg[11]),
        .O(i__carry_i_11__0_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_11__1
       (.I0(\PWM_Out_reg[3]_0 [10]),
        .I1(counter_reg[10]),
        .I2(\PWM_Out_reg[3]_0 [11]),
        .I3(counter_reg[11]),
        .O(i__carry_i_11__1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_12
       (.I0(\PWM_Out_reg[1]_0 [8]),
        .I1(counter_reg[8]),
        .I2(\PWM_Out_reg[1]_0 [9]),
        .I3(counter_reg[9]),
        .O(i__carry_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_12__0
       (.I0(\PWM_Out_reg[2]_0 [8]),
        .I1(counter_reg[8]),
        .I2(\PWM_Out_reg[2]_0 [9]),
        .I3(counter_reg[9]),
        .O(i__carry_i_12__0_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_12__1
       (.I0(\PWM_Out_reg[3]_0 [8]),
        .I1(counter_reg[8]),
        .I2(\PWM_Out_reg[3]_0 [9]),
        .I3(counter_reg[9]),
        .O(i__carry_i_12__1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_13
       (.I0(\PWM_Out_reg[1]_0 [6]),
        .I1(counter_reg[6]),
        .I2(\PWM_Out_reg[1]_0 [7]),
        .I3(counter_reg[7]),
        .O(i__carry_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_13__0
       (.I0(\PWM_Out_reg[2]_0 [6]),
        .I1(counter_reg[6]),
        .I2(\PWM_Out_reg[2]_0 [7]),
        .I3(counter_reg[7]),
        .O(i__carry_i_13__0_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_13__1
       (.I0(\PWM_Out_reg[3]_0 [6]),
        .I1(counter_reg[6]),
        .I2(\PWM_Out_reg[3]_0 [7]),
        .I3(counter_reg[7]),
        .O(i__carry_i_13__1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_14
       (.I0(\PWM_Out_reg[1]_0 [4]),
        .I1(counter_reg[4]),
        .I2(\PWM_Out_reg[1]_0 [5]),
        .I3(counter_reg[5]),
        .O(i__carry_i_14_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_14__0
       (.I0(\PWM_Out_reg[2]_0 [4]),
        .I1(counter_reg[4]),
        .I2(\PWM_Out_reg[2]_0 [5]),
        .I3(counter_reg[5]),
        .O(i__carry_i_14__0_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_14__1
       (.I0(\PWM_Out_reg[3]_0 [4]),
        .I1(counter_reg[4]),
        .I2(\PWM_Out_reg[3]_0 [5]),
        .I3(counter_reg[5]),
        .O(i__carry_i_14__1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_15
       (.I0(\PWM_Out_reg[1]_0 [2]),
        .I1(counter_reg[2]),
        .I2(\PWM_Out_reg[1]_0 [3]),
        .I3(counter_reg[3]),
        .O(i__carry_i_15_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_15__0
       (.I0(\PWM_Out_reg[2]_0 [2]),
        .I1(counter_reg[2]),
        .I2(\PWM_Out_reg[2]_0 [3]),
        .I3(counter_reg[3]),
        .O(i__carry_i_15__0_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_15__1
       (.I0(\PWM_Out_reg[3]_0 [2]),
        .I1(counter_reg[2]),
        .I2(\PWM_Out_reg[3]_0 [3]),
        .I3(counter_reg[3]),
        .O(i__carry_i_15__1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_16
       (.I0(\PWM_Out_reg[1]_0 [0]),
        .I1(counter_reg[0]),
        .I2(\PWM_Out_reg[1]_0 [1]),
        .I3(counter_reg[1]),
        .O(i__carry_i_16_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_16__0
       (.I0(\PWM_Out_reg[2]_0 [0]),
        .I1(counter_reg[0]),
        .I2(\PWM_Out_reg[2]_0 [1]),
        .I3(counter_reg[1]),
        .O(i__carry_i_16__0_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_16__1
       (.I0(\PWM_Out_reg[3]_0 [0]),
        .I1(counter_reg[0]),
        .I2(\PWM_Out_reg[3]_0 [1]),
        .I3(counter_reg[1]),
        .O(i__carry_i_16__1_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_1__0
       (.I0(\PWM_Out_reg[2]_0 [14]),
        .I1(counter_reg[14]),
        .I2(counter_reg[15]),
        .I3(\PWM_Out_reg[2]_0 [15]),
        .O(i__carry_i_1__0_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_1__1
       (.I0(\PWM_Out_reg[3]_0 [14]),
        .I1(counter_reg[14]),
        .I2(counter_reg[15]),
        .I3(\PWM_Out_reg[3]_0 [15]),
        .O(i__carry_i_1__1_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_2
       (.I0(\PWM_Out_reg[1]_0 [12]),
        .I1(counter_reg[12]),
        .I2(counter_reg[13]),
        .I3(\PWM_Out_reg[1]_0 [13]),
        .O(i__carry_i_2_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_2__0
       (.I0(\PWM_Out_reg[2]_0 [12]),
        .I1(counter_reg[12]),
        .I2(counter_reg[13]),
        .I3(\PWM_Out_reg[2]_0 [13]),
        .O(i__carry_i_2__0_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_2__1
       (.I0(\PWM_Out_reg[3]_0 [12]),
        .I1(counter_reg[12]),
        .I2(counter_reg[13]),
        .I3(\PWM_Out_reg[3]_0 [13]),
        .O(i__carry_i_2__1_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_3
       (.I0(\PWM_Out_reg[1]_0 [10]),
        .I1(counter_reg[10]),
        .I2(counter_reg[11]),
        .I3(\PWM_Out_reg[1]_0 [11]),
        .O(i__carry_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_3__0
       (.I0(\PWM_Out_reg[2]_0 [10]),
        .I1(counter_reg[10]),
        .I2(counter_reg[11]),
        .I3(\PWM_Out_reg[2]_0 [11]),
        .O(i__carry_i_3__0_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_3__1
       (.I0(\PWM_Out_reg[3]_0 [10]),
        .I1(counter_reg[10]),
        .I2(counter_reg[11]),
        .I3(\PWM_Out_reg[3]_0 [11]),
        .O(i__carry_i_3__1_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_4
       (.I0(\PWM_Out_reg[1]_0 [8]),
        .I1(counter_reg[8]),
        .I2(counter_reg[9]),
        .I3(\PWM_Out_reg[1]_0 [9]),
        .O(i__carry_i_4_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_4__0
       (.I0(\PWM_Out_reg[2]_0 [8]),
        .I1(counter_reg[8]),
        .I2(counter_reg[9]),
        .I3(\PWM_Out_reg[2]_0 [9]),
        .O(i__carry_i_4__0_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_4__1
       (.I0(\PWM_Out_reg[3]_0 [8]),
        .I1(counter_reg[8]),
        .I2(counter_reg[9]),
        .I3(\PWM_Out_reg[3]_0 [9]),
        .O(i__carry_i_4__1_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_5
       (.I0(\PWM_Out_reg[1]_0 [6]),
        .I1(counter_reg[6]),
        .I2(counter_reg[7]),
        .I3(\PWM_Out_reg[1]_0 [7]),
        .O(i__carry_i_5_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_5__0
       (.I0(\PWM_Out_reg[2]_0 [6]),
        .I1(counter_reg[6]),
        .I2(counter_reg[7]),
        .I3(\PWM_Out_reg[2]_0 [7]),
        .O(i__carry_i_5__0_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_5__1
       (.I0(\PWM_Out_reg[3]_0 [6]),
        .I1(counter_reg[6]),
        .I2(counter_reg[7]),
        .I3(\PWM_Out_reg[3]_0 [7]),
        .O(i__carry_i_5__1_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_6
       (.I0(\PWM_Out_reg[1]_0 [4]),
        .I1(counter_reg[4]),
        .I2(counter_reg[5]),
        .I3(\PWM_Out_reg[1]_0 [5]),
        .O(i__carry_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_6__0
       (.I0(\PWM_Out_reg[2]_0 [4]),
        .I1(counter_reg[4]),
        .I2(counter_reg[5]),
        .I3(\PWM_Out_reg[2]_0 [5]),
        .O(i__carry_i_6__0_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_6__1
       (.I0(\PWM_Out_reg[3]_0 [4]),
        .I1(counter_reg[4]),
        .I2(counter_reg[5]),
        .I3(\PWM_Out_reg[3]_0 [5]),
        .O(i__carry_i_6__1_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_7
       (.I0(\PWM_Out_reg[1]_0 [2]),
        .I1(counter_reg[2]),
        .I2(counter_reg[3]),
        .I3(\PWM_Out_reg[1]_0 [3]),
        .O(i__carry_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_7__0
       (.I0(\PWM_Out_reg[2]_0 [2]),
        .I1(counter_reg[2]),
        .I2(counter_reg[3]),
        .I3(\PWM_Out_reg[2]_0 [3]),
        .O(i__carry_i_7__0_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_7__1
       (.I0(\PWM_Out_reg[3]_0 [2]),
        .I1(counter_reg[2]),
        .I2(counter_reg[3]),
        .I3(\PWM_Out_reg[3]_0 [3]),
        .O(i__carry_i_7__1_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_8
       (.I0(\PWM_Out_reg[1]_0 [0]),
        .I1(counter_reg[0]),
        .I2(counter_reg[1]),
        .I3(\PWM_Out_reg[1]_0 [1]),
        .O(i__carry_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_8__0
       (.I0(\PWM_Out_reg[2]_0 [0]),
        .I1(counter_reg[0]),
        .I2(counter_reg[1]),
        .I3(\PWM_Out_reg[2]_0 [1]),
        .O(i__carry_i_8__0_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    i__carry_i_8__1
       (.I0(\PWM_Out_reg[3]_0 [0]),
        .I1(counter_reg[0]),
        .I2(counter_reg[1]),
        .I3(\PWM_Out_reg[3]_0 [1]),
        .O(i__carry_i_8__1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_9
       (.I0(\PWM_Out_reg[1]_0 [14]),
        .I1(counter_reg[14]),
        .I2(\PWM_Out_reg[1]_0 [15]),
        .I3(counter_reg[15]),
        .O(i__carry_i_9_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_9__0
       (.I0(\PWM_Out_reg[2]_0 [14]),
        .I1(counter_reg[14]),
        .I2(\PWM_Out_reg[2]_0 [15]),
        .I3(counter_reg[15]),
        .O(i__carry_i_9__0_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_9__1
       (.I0(\PWM_Out_reg[3]_0 [14]),
        .I1(counter_reg[14]),
        .I2(\PWM_Out_reg[3]_0 [15]),
        .I3(counter_reg[15]),
        .O(i__carry_i_9__1_n_0));
endmodule

(* ORIG_REF_NAME = "PWM_v1_0" *) 
module design_1_PWM_0_0_PWM_v1_0
   (S_AXI_WREADY,
    S_AXI_AWREADY,
    S_AXI_ARREADY,
    pwm_axi_rdata,
    PWM_Out,
    pwm_axi_rvalid,
    pwm_axi_bvalid,
    pwm_axi_aclk,
    pwm_axi_awaddr,
    pwm_axi_wdata,
    pwm_axi_araddr,
    pwm_axi_awvalid,
    pwm_axi_wvalid,
    pwm_axi_wstrb,
    pwm_axi_arvalid,
    pwm_axi_aresetn,
    pwm_axi_bready,
    pwm_axi_rready);
  output S_AXI_WREADY;
  output S_AXI_AWREADY;
  output S_AXI_ARREADY;
  output [31:0]pwm_axi_rdata;
  output [3:0]PWM_Out;
  output pwm_axi_rvalid;
  output pwm_axi_bvalid;
  input pwm_axi_aclk;
  input [2:0]pwm_axi_awaddr;
  input [31:0]pwm_axi_wdata;
  input [2:0]pwm_axi_araddr;
  input pwm_axi_awvalid;
  input pwm_axi_wvalid;
  input [3:0]pwm_axi_wstrb;
  input pwm_axi_arvalid;
  input pwm_axi_aresetn;
  input pwm_axi_bready;
  input pwm_axi_rready;

  wire [3:0]PWM_Out;
  wire S_AXI_ARREADY;
  wire S_AXI_AWREADY;
  wire S_AXI_WREADY;
  wire pwm_axi_aclk;
  wire [2:0]pwm_axi_araddr;
  wire pwm_axi_aresetn;
  wire pwm_axi_arvalid;
  wire [2:0]pwm_axi_awaddr;
  wire pwm_axi_awvalid;
  wire pwm_axi_bready;
  wire pwm_axi_bvalid;
  wire [31:0]pwm_axi_rdata;
  wire pwm_axi_rready;
  wire pwm_axi_rvalid;
  wire [31:0]pwm_axi_wdata;
  wire [3:0]pwm_axi_wstrb;
  wire pwm_axi_wvalid;

  design_1_PWM_0_0_PWM_v1_0_PWM_AXI PWM_v1_0_PWM_AXI_inst
       (.PWM_Out(PWM_Out),
        .S_AXI_ARREADY(S_AXI_ARREADY),
        .S_AXI_AWREADY(S_AXI_AWREADY),
        .S_AXI_WREADY(S_AXI_WREADY),
        .pwm_axi_aclk(pwm_axi_aclk),
        .pwm_axi_araddr(pwm_axi_araddr),
        .pwm_axi_aresetn(pwm_axi_aresetn),
        .pwm_axi_arvalid(pwm_axi_arvalid),
        .pwm_axi_awaddr(pwm_axi_awaddr),
        .pwm_axi_awvalid(pwm_axi_awvalid),
        .pwm_axi_bready(pwm_axi_bready),
        .pwm_axi_bvalid(pwm_axi_bvalid),
        .pwm_axi_rdata(pwm_axi_rdata),
        .pwm_axi_rready(pwm_axi_rready),
        .pwm_axi_rvalid(pwm_axi_rvalid),
        .pwm_axi_wdata(pwm_axi_wdata),
        .pwm_axi_wstrb(pwm_axi_wstrb),
        .pwm_axi_wvalid(pwm_axi_wvalid));
endmodule

(* ORIG_REF_NAME = "PWM_v1_0_PWM_AXI" *) 
module design_1_PWM_0_0_PWM_v1_0_PWM_AXI
   (S_AXI_WREADY,
    S_AXI_AWREADY,
    S_AXI_ARREADY,
    pwm_axi_rdata,
    PWM_Out,
    pwm_axi_rvalid,
    pwm_axi_bvalid,
    pwm_axi_aclk,
    pwm_axi_awaddr,
    pwm_axi_wdata,
    pwm_axi_araddr,
    pwm_axi_awvalid,
    pwm_axi_wvalid,
    pwm_axi_wstrb,
    pwm_axi_arvalid,
    pwm_axi_aresetn,
    pwm_axi_bready,
    pwm_axi_rready);
  output S_AXI_WREADY;
  output S_AXI_AWREADY;
  output S_AXI_ARREADY;
  output [31:0]pwm_axi_rdata;
  output [3:0]PWM_Out;
  output pwm_axi_rvalid;
  output pwm_axi_bvalid;
  input pwm_axi_aclk;
  input [2:0]pwm_axi_awaddr;
  input [31:0]pwm_axi_wdata;
  input [2:0]pwm_axi_araddr;
  input pwm_axi_awvalid;
  input pwm_axi_wvalid;
  input [3:0]pwm_axi_wstrb;
  input pwm_axi_arvalid;
  input pwm_axi_aresetn;
  input pwm_axi_bready;
  input pwm_axi_rready;

  wire [3:0]PWM_Out;
  wire S_AXI_ARREADY;
  wire S_AXI_AWREADY;
  wire S_AXI_WREADY;
  wire aw_en_i_1_n_0;
  wire aw_en_reg_n_0;
  wire axi_arready0;
  wire axi_awready0;
  wire axi_awready_i_1_n_0;
  wire axi_bvalid_i_1_n_0;
  wire \axi_rdata[0]_i_2_n_0 ;
  wire \axi_rdata[10]_i_2_n_0 ;
  wire \axi_rdata[11]_i_2_n_0 ;
  wire \axi_rdata[12]_i_2_n_0 ;
  wire \axi_rdata[13]_i_2_n_0 ;
  wire \axi_rdata[14]_i_2_n_0 ;
  wire \axi_rdata[15]_i_2_n_0 ;
  wire \axi_rdata[16]_i_2_n_0 ;
  wire \axi_rdata[17]_i_2_n_0 ;
  wire \axi_rdata[18]_i_2_n_0 ;
  wire \axi_rdata[19]_i_2_n_0 ;
  wire \axi_rdata[1]_i_2_n_0 ;
  wire \axi_rdata[20]_i_2_n_0 ;
  wire \axi_rdata[21]_i_2_n_0 ;
  wire \axi_rdata[22]_i_2_n_0 ;
  wire \axi_rdata[23]_i_2_n_0 ;
  wire \axi_rdata[24]_i_2_n_0 ;
  wire \axi_rdata[25]_i_2_n_0 ;
  wire \axi_rdata[26]_i_2_n_0 ;
  wire \axi_rdata[27]_i_2_n_0 ;
  wire \axi_rdata[28]_i_2_n_0 ;
  wire \axi_rdata[29]_i_2_n_0 ;
  wire \axi_rdata[2]_i_2_n_0 ;
  wire \axi_rdata[30]_i_2_n_0 ;
  wire \axi_rdata[31]_i_2_n_0 ;
  wire \axi_rdata[3]_i_2_n_0 ;
  wire \axi_rdata[4]_i_2_n_0 ;
  wire \axi_rdata[5]_i_2_n_0 ;
  wire \axi_rdata[6]_i_2_n_0 ;
  wire \axi_rdata[7]_i_2_n_0 ;
  wire \axi_rdata[8]_i_2_n_0 ;
  wire \axi_rdata[9]_i_2_n_0 ;
  wire axi_rvalid_i_1_n_0;
  wire axi_wready0;
  wire [2:0]p_0_in;
  wire [31:7]p_1_in;
  wire pwm_axi_aclk;
  wire [2:0]pwm_axi_araddr;
  wire pwm_axi_aresetn;
  wire pwm_axi_arvalid;
  wire [2:0]pwm_axi_awaddr;
  wire pwm_axi_awvalid;
  wire pwm_axi_bready;
  wire pwm_axi_bvalid;
  wire [31:0]pwm_axi_rdata;
  wire pwm_axi_rready;
  wire pwm_axi_rvalid;
  wire [31:0]pwm_axi_wdata;
  wire [3:0]pwm_axi_wstrb;
  wire pwm_axi_wvalid;
  wire [31:0]reg_data_out;
  wire [2:0]sel0;
  wire [31:0]slv_reg0;
  wire [31:0]slv_reg1;
  wire \slv_reg1[15]_i_1_n_0 ;
  wire \slv_reg1[23]_i_1_n_0 ;
  wire \slv_reg1[31]_i_1_n_0 ;
  wire \slv_reg1[7]_i_1_n_0 ;
  wire [31:0]slv_reg2;
  wire \slv_reg2[15]_i_1_n_0 ;
  wire \slv_reg2[23]_i_1_n_0 ;
  wire \slv_reg2[31]_i_1_n_0 ;
  wire \slv_reg2[7]_i_1_n_0 ;
  wire [31:0]slv_reg3;
  wire \slv_reg3[15]_i_1_n_0 ;
  wire \slv_reg3[23]_i_1_n_0 ;
  wire \slv_reg3[31]_i_1_n_0 ;
  wire \slv_reg3[7]_i_1_n_0 ;
  wire [31:0]slv_reg4;
  wire \slv_reg4[15]_i_1_n_0 ;
  wire \slv_reg4[23]_i_1_n_0 ;
  wire \slv_reg4[31]_i_1_n_0 ;
  wire \slv_reg4[7]_i_1_n_0 ;
  wire slv_reg_rden__0;
  wire slv_reg_wren__0;

  design_1_PWM_0_0_PWM_Logic PWM_Logic_inst
       (.PWM_Out(PWM_Out),
        .\PWM_Out_reg[0]_0 (slv_reg0),
        .\PWM_Out_reg[1]_0 (slv_reg1),
        .\PWM_Out_reg[2]_0 (slv_reg2),
        .\PWM_Out_reg[3]_0 (slv_reg3),
        .Q(slv_reg4),
        .pwm_axi_aclk(pwm_axi_aclk));
  LUT6 #(
    .INIT(64'hF7FFC4CCC4CCC4CC)) 
    aw_en_i_1
       (.I0(pwm_axi_awvalid),
        .I1(aw_en_reg_n_0),
        .I2(S_AXI_AWREADY),
        .I3(pwm_axi_wvalid),
        .I4(pwm_axi_bready),
        .I5(pwm_axi_bvalid),
        .O(aw_en_i_1_n_0));
  FDSE aw_en_reg
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(aw_en_i_1_n_0),
        .Q(aw_en_reg_n_0),
        .S(axi_awready_i_1_n_0));
  FDRE \axi_araddr_reg[2] 
       (.C(pwm_axi_aclk),
        .CE(axi_arready0),
        .D(pwm_axi_araddr[0]),
        .Q(sel0[0]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_araddr_reg[3] 
       (.C(pwm_axi_aclk),
        .CE(axi_arready0),
        .D(pwm_axi_araddr[1]),
        .Q(sel0[1]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_araddr_reg[4] 
       (.C(pwm_axi_aclk),
        .CE(axi_arready0),
        .D(pwm_axi_araddr[2]),
        .Q(sel0[2]),
        .R(axi_awready_i_1_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    axi_arready_i_1
       (.I0(pwm_axi_arvalid),
        .I1(S_AXI_ARREADY),
        .O(axi_arready0));
  FDRE axi_arready_reg
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(axi_arready0),
        .Q(S_AXI_ARREADY),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_awaddr_reg[2] 
       (.C(pwm_axi_aclk),
        .CE(axi_awready0),
        .D(pwm_axi_awaddr[0]),
        .Q(p_0_in[0]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_awaddr_reg[3] 
       (.C(pwm_axi_aclk),
        .CE(axi_awready0),
        .D(pwm_axi_awaddr[1]),
        .Q(p_0_in[1]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_awaddr_reg[4] 
       (.C(pwm_axi_aclk),
        .CE(axi_awready0),
        .D(pwm_axi_awaddr[2]),
        .Q(p_0_in[2]),
        .R(axi_awready_i_1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    axi_awready_i_1
       (.I0(pwm_axi_aresetn),
        .O(axi_awready_i_1_n_0));
  LUT4 #(
    .INIT(16'h2000)) 
    axi_awready_i_2
       (.I0(pwm_axi_wvalid),
        .I1(S_AXI_AWREADY),
        .I2(aw_en_reg_n_0),
        .I3(pwm_axi_awvalid),
        .O(axi_awready0));
  FDRE axi_awready_reg
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(axi_awready0),
        .Q(S_AXI_AWREADY),
        .R(axi_awready_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000FFFF80008000)) 
    axi_bvalid_i_1
       (.I0(pwm_axi_awvalid),
        .I1(pwm_axi_wvalid),
        .I2(S_AXI_AWREADY),
        .I3(S_AXI_WREADY),
        .I4(pwm_axi_bready),
        .I5(pwm_axi_bvalid),
        .O(axi_bvalid_i_1_n_0));
  FDRE axi_bvalid_reg
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(axi_bvalid_i_1_n_0),
        .Q(pwm_axi_bvalid),
        .R(axi_awready_i_1_n_0));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[0]_i_1 
       (.I0(\axi_rdata[0]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[0]),
        .I4(sel0[0]),
        .O(reg_data_out[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[0]_i_2 
       (.I0(slv_reg3[0]),
        .I1(slv_reg2[0]),
        .I2(sel0[1]),
        .I3(slv_reg1[0]),
        .I4(sel0[0]),
        .I5(slv_reg0[0]),
        .O(\axi_rdata[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[10]_i_1 
       (.I0(\axi_rdata[10]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[10]),
        .I4(sel0[0]),
        .O(reg_data_out[10]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[10]_i_2 
       (.I0(slv_reg3[10]),
        .I1(slv_reg2[10]),
        .I2(sel0[1]),
        .I3(slv_reg1[10]),
        .I4(sel0[0]),
        .I5(slv_reg0[10]),
        .O(\axi_rdata[10]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[11]_i_1 
       (.I0(\axi_rdata[11]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[11]),
        .I4(sel0[0]),
        .O(reg_data_out[11]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[11]_i_2 
       (.I0(slv_reg3[11]),
        .I1(slv_reg2[11]),
        .I2(sel0[1]),
        .I3(slv_reg1[11]),
        .I4(sel0[0]),
        .I5(slv_reg0[11]),
        .O(\axi_rdata[11]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[12]_i_1 
       (.I0(\axi_rdata[12]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[12]),
        .I4(sel0[0]),
        .O(reg_data_out[12]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[12]_i_2 
       (.I0(slv_reg3[12]),
        .I1(slv_reg2[12]),
        .I2(sel0[1]),
        .I3(slv_reg1[12]),
        .I4(sel0[0]),
        .I5(slv_reg0[12]),
        .O(\axi_rdata[12]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[13]_i_1 
       (.I0(\axi_rdata[13]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[13]),
        .I4(sel0[0]),
        .O(reg_data_out[13]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[13]_i_2 
       (.I0(slv_reg3[13]),
        .I1(slv_reg2[13]),
        .I2(sel0[1]),
        .I3(slv_reg1[13]),
        .I4(sel0[0]),
        .I5(slv_reg0[13]),
        .O(\axi_rdata[13]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[14]_i_1 
       (.I0(\axi_rdata[14]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[14]),
        .I4(sel0[0]),
        .O(reg_data_out[14]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[14]_i_2 
       (.I0(slv_reg3[14]),
        .I1(slv_reg2[14]),
        .I2(sel0[1]),
        .I3(slv_reg1[14]),
        .I4(sel0[0]),
        .I5(slv_reg0[14]),
        .O(\axi_rdata[14]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[15]_i_1 
       (.I0(\axi_rdata[15]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[15]),
        .I4(sel0[0]),
        .O(reg_data_out[15]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[15]_i_2 
       (.I0(slv_reg3[15]),
        .I1(slv_reg2[15]),
        .I2(sel0[1]),
        .I3(slv_reg1[15]),
        .I4(sel0[0]),
        .I5(slv_reg0[15]),
        .O(\axi_rdata[15]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[16]_i_1 
       (.I0(\axi_rdata[16]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[16]),
        .I4(sel0[0]),
        .O(reg_data_out[16]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[16]_i_2 
       (.I0(slv_reg3[16]),
        .I1(slv_reg2[16]),
        .I2(sel0[1]),
        .I3(slv_reg1[16]),
        .I4(sel0[0]),
        .I5(slv_reg0[16]),
        .O(\axi_rdata[16]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[17]_i_1 
       (.I0(\axi_rdata[17]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[17]),
        .I4(sel0[0]),
        .O(reg_data_out[17]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[17]_i_2 
       (.I0(slv_reg3[17]),
        .I1(slv_reg2[17]),
        .I2(sel0[1]),
        .I3(slv_reg1[17]),
        .I4(sel0[0]),
        .I5(slv_reg0[17]),
        .O(\axi_rdata[17]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[18]_i_1 
       (.I0(\axi_rdata[18]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[18]),
        .I4(sel0[0]),
        .O(reg_data_out[18]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[18]_i_2 
       (.I0(slv_reg3[18]),
        .I1(slv_reg2[18]),
        .I2(sel0[1]),
        .I3(slv_reg1[18]),
        .I4(sel0[0]),
        .I5(slv_reg0[18]),
        .O(\axi_rdata[18]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[19]_i_1 
       (.I0(\axi_rdata[19]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[19]),
        .I4(sel0[0]),
        .O(reg_data_out[19]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[19]_i_2 
       (.I0(slv_reg3[19]),
        .I1(slv_reg2[19]),
        .I2(sel0[1]),
        .I3(slv_reg1[19]),
        .I4(sel0[0]),
        .I5(slv_reg0[19]),
        .O(\axi_rdata[19]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[1]_i_1 
       (.I0(\axi_rdata[1]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[1]),
        .I4(sel0[0]),
        .O(reg_data_out[1]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[1]_i_2 
       (.I0(slv_reg3[1]),
        .I1(slv_reg2[1]),
        .I2(sel0[1]),
        .I3(slv_reg1[1]),
        .I4(sel0[0]),
        .I5(slv_reg0[1]),
        .O(\axi_rdata[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[20]_i_1 
       (.I0(\axi_rdata[20]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[20]),
        .I4(sel0[0]),
        .O(reg_data_out[20]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[20]_i_2 
       (.I0(slv_reg3[20]),
        .I1(slv_reg2[20]),
        .I2(sel0[1]),
        .I3(slv_reg1[20]),
        .I4(sel0[0]),
        .I5(slv_reg0[20]),
        .O(\axi_rdata[20]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[21]_i_1 
       (.I0(\axi_rdata[21]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[21]),
        .I4(sel0[0]),
        .O(reg_data_out[21]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[21]_i_2 
       (.I0(slv_reg3[21]),
        .I1(slv_reg2[21]),
        .I2(sel0[1]),
        .I3(slv_reg1[21]),
        .I4(sel0[0]),
        .I5(slv_reg0[21]),
        .O(\axi_rdata[21]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[22]_i_1 
       (.I0(\axi_rdata[22]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[22]),
        .I4(sel0[0]),
        .O(reg_data_out[22]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[22]_i_2 
       (.I0(slv_reg3[22]),
        .I1(slv_reg2[22]),
        .I2(sel0[1]),
        .I3(slv_reg1[22]),
        .I4(sel0[0]),
        .I5(slv_reg0[22]),
        .O(\axi_rdata[22]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[23]_i_1 
       (.I0(\axi_rdata[23]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[23]),
        .I4(sel0[0]),
        .O(reg_data_out[23]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[23]_i_2 
       (.I0(slv_reg3[23]),
        .I1(slv_reg2[23]),
        .I2(sel0[1]),
        .I3(slv_reg1[23]),
        .I4(sel0[0]),
        .I5(slv_reg0[23]),
        .O(\axi_rdata[23]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[24]_i_1 
       (.I0(\axi_rdata[24]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[24]),
        .I4(sel0[0]),
        .O(reg_data_out[24]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[24]_i_2 
       (.I0(slv_reg3[24]),
        .I1(slv_reg2[24]),
        .I2(sel0[1]),
        .I3(slv_reg1[24]),
        .I4(sel0[0]),
        .I5(slv_reg0[24]),
        .O(\axi_rdata[24]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[25]_i_1 
       (.I0(\axi_rdata[25]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[25]),
        .I4(sel0[0]),
        .O(reg_data_out[25]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[25]_i_2 
       (.I0(slv_reg3[25]),
        .I1(slv_reg2[25]),
        .I2(sel0[1]),
        .I3(slv_reg1[25]),
        .I4(sel0[0]),
        .I5(slv_reg0[25]),
        .O(\axi_rdata[25]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[26]_i_1 
       (.I0(\axi_rdata[26]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[26]),
        .I4(sel0[0]),
        .O(reg_data_out[26]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[26]_i_2 
       (.I0(slv_reg3[26]),
        .I1(slv_reg2[26]),
        .I2(sel0[1]),
        .I3(slv_reg1[26]),
        .I4(sel0[0]),
        .I5(slv_reg0[26]),
        .O(\axi_rdata[26]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[27]_i_1 
       (.I0(\axi_rdata[27]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[27]),
        .I4(sel0[0]),
        .O(reg_data_out[27]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[27]_i_2 
       (.I0(slv_reg3[27]),
        .I1(slv_reg2[27]),
        .I2(sel0[1]),
        .I3(slv_reg1[27]),
        .I4(sel0[0]),
        .I5(slv_reg0[27]),
        .O(\axi_rdata[27]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[28]_i_1 
       (.I0(\axi_rdata[28]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[28]),
        .I4(sel0[0]),
        .O(reg_data_out[28]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[28]_i_2 
       (.I0(slv_reg3[28]),
        .I1(slv_reg2[28]),
        .I2(sel0[1]),
        .I3(slv_reg1[28]),
        .I4(sel0[0]),
        .I5(slv_reg0[28]),
        .O(\axi_rdata[28]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[29]_i_1 
       (.I0(\axi_rdata[29]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[29]),
        .I4(sel0[0]),
        .O(reg_data_out[29]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[29]_i_2 
       (.I0(slv_reg3[29]),
        .I1(slv_reg2[29]),
        .I2(sel0[1]),
        .I3(slv_reg1[29]),
        .I4(sel0[0]),
        .I5(slv_reg0[29]),
        .O(\axi_rdata[29]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[2]_i_1 
       (.I0(\axi_rdata[2]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[2]),
        .I4(sel0[0]),
        .O(reg_data_out[2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[2]_i_2 
       (.I0(slv_reg3[2]),
        .I1(slv_reg2[2]),
        .I2(sel0[1]),
        .I3(slv_reg1[2]),
        .I4(sel0[0]),
        .I5(slv_reg0[2]),
        .O(\axi_rdata[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[30]_i_1 
       (.I0(\axi_rdata[30]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[30]),
        .I4(sel0[0]),
        .O(reg_data_out[30]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[30]_i_2 
       (.I0(slv_reg3[30]),
        .I1(slv_reg2[30]),
        .I2(sel0[1]),
        .I3(slv_reg1[30]),
        .I4(sel0[0]),
        .I5(slv_reg0[30]),
        .O(\axi_rdata[30]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[31]_i_1 
       (.I0(\axi_rdata[31]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[31]),
        .I4(sel0[0]),
        .O(reg_data_out[31]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[31]_i_2 
       (.I0(slv_reg3[31]),
        .I1(slv_reg2[31]),
        .I2(sel0[1]),
        .I3(slv_reg1[31]),
        .I4(sel0[0]),
        .I5(slv_reg0[31]),
        .O(\axi_rdata[31]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[3]_i_1 
       (.I0(\axi_rdata[3]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[3]),
        .I4(sel0[0]),
        .O(reg_data_out[3]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[3]_i_2 
       (.I0(slv_reg3[3]),
        .I1(slv_reg2[3]),
        .I2(sel0[1]),
        .I3(slv_reg1[3]),
        .I4(sel0[0]),
        .I5(slv_reg0[3]),
        .O(\axi_rdata[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[4]_i_1 
       (.I0(\axi_rdata[4]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[4]),
        .I4(sel0[0]),
        .O(reg_data_out[4]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[4]_i_2 
       (.I0(slv_reg3[4]),
        .I1(slv_reg2[4]),
        .I2(sel0[1]),
        .I3(slv_reg1[4]),
        .I4(sel0[0]),
        .I5(slv_reg0[4]),
        .O(\axi_rdata[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[5]_i_1 
       (.I0(\axi_rdata[5]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[5]),
        .I4(sel0[0]),
        .O(reg_data_out[5]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[5]_i_2 
       (.I0(slv_reg3[5]),
        .I1(slv_reg2[5]),
        .I2(sel0[1]),
        .I3(slv_reg1[5]),
        .I4(sel0[0]),
        .I5(slv_reg0[5]),
        .O(\axi_rdata[5]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[6]_i_1 
       (.I0(\axi_rdata[6]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[6]),
        .I4(sel0[0]),
        .O(reg_data_out[6]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[6]_i_2 
       (.I0(slv_reg3[6]),
        .I1(slv_reg2[6]),
        .I2(sel0[1]),
        .I3(slv_reg1[6]),
        .I4(sel0[0]),
        .I5(slv_reg0[6]),
        .O(\axi_rdata[6]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[7]_i_1 
       (.I0(\axi_rdata[7]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[7]),
        .I4(sel0[0]),
        .O(reg_data_out[7]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[7]_i_2 
       (.I0(slv_reg3[7]),
        .I1(slv_reg2[7]),
        .I2(sel0[1]),
        .I3(slv_reg1[7]),
        .I4(sel0[0]),
        .I5(slv_reg0[7]),
        .O(\axi_rdata[7]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[8]_i_1 
       (.I0(\axi_rdata[8]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[8]),
        .I4(sel0[0]),
        .O(reg_data_out[8]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[8]_i_2 
       (.I0(slv_reg3[8]),
        .I1(slv_reg2[8]),
        .I2(sel0[1]),
        .I3(slv_reg1[8]),
        .I4(sel0[0]),
        .I5(slv_reg0[8]),
        .O(\axi_rdata[8]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A3A0A)) 
    \axi_rdata[9]_i_1 
       (.I0(\axi_rdata[9]_i_2_n_0 ),
        .I1(sel0[1]),
        .I2(sel0[2]),
        .I3(slv_reg4[9]),
        .I4(sel0[0]),
        .O(reg_data_out[9]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \axi_rdata[9]_i_2 
       (.I0(slv_reg3[9]),
        .I1(slv_reg2[9]),
        .I2(sel0[1]),
        .I3(slv_reg1[9]),
        .I4(sel0[0]),
        .I5(slv_reg0[9]),
        .O(\axi_rdata[9]_i_2_n_0 ));
  FDRE \axi_rdata_reg[0] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[0]),
        .Q(pwm_axi_rdata[0]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[10] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[10]),
        .Q(pwm_axi_rdata[10]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[11] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[11]),
        .Q(pwm_axi_rdata[11]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[12] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[12]),
        .Q(pwm_axi_rdata[12]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[13] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[13]),
        .Q(pwm_axi_rdata[13]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[14] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[14]),
        .Q(pwm_axi_rdata[14]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[15] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[15]),
        .Q(pwm_axi_rdata[15]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[16] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[16]),
        .Q(pwm_axi_rdata[16]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[17] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[17]),
        .Q(pwm_axi_rdata[17]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[18] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[18]),
        .Q(pwm_axi_rdata[18]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[19] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[19]),
        .Q(pwm_axi_rdata[19]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[1] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[1]),
        .Q(pwm_axi_rdata[1]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[20] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[20]),
        .Q(pwm_axi_rdata[20]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[21] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[21]),
        .Q(pwm_axi_rdata[21]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[22] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[22]),
        .Q(pwm_axi_rdata[22]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[23] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[23]),
        .Q(pwm_axi_rdata[23]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[24] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[24]),
        .Q(pwm_axi_rdata[24]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[25] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[25]),
        .Q(pwm_axi_rdata[25]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[26] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[26]),
        .Q(pwm_axi_rdata[26]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[27] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[27]),
        .Q(pwm_axi_rdata[27]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[28] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[28]),
        .Q(pwm_axi_rdata[28]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[29] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[29]),
        .Q(pwm_axi_rdata[29]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[2] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[2]),
        .Q(pwm_axi_rdata[2]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[30] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[30]),
        .Q(pwm_axi_rdata[30]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[31] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[31]),
        .Q(pwm_axi_rdata[31]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[3] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[3]),
        .Q(pwm_axi_rdata[3]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[4] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[4]),
        .Q(pwm_axi_rdata[4]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[5] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[5]),
        .Q(pwm_axi_rdata[5]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[6] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[6]),
        .Q(pwm_axi_rdata[6]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[7] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[7]),
        .Q(pwm_axi_rdata[7]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[8] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[8]),
        .Q(pwm_axi_rdata[8]),
        .R(axi_awready_i_1_n_0));
  FDRE \axi_rdata_reg[9] 
       (.C(pwm_axi_aclk),
        .CE(slv_reg_rden__0),
        .D(reg_data_out[9]),
        .Q(pwm_axi_rdata[9]),
        .R(axi_awready_i_1_n_0));
  LUT4 #(
    .INIT(16'h08F8)) 
    axi_rvalid_i_1
       (.I0(S_AXI_ARREADY),
        .I1(pwm_axi_arvalid),
        .I2(pwm_axi_rvalid),
        .I3(pwm_axi_rready),
        .O(axi_rvalid_i_1_n_0));
  FDRE axi_rvalid_reg
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(axi_rvalid_i_1_n_0),
        .Q(pwm_axi_rvalid),
        .R(axi_awready_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'h0800)) 
    axi_wready_i_1
       (.I0(pwm_axi_awvalid),
        .I1(pwm_axi_wvalid),
        .I2(S_AXI_WREADY),
        .I3(aw_en_reg_n_0),
        .O(axi_wready0));
  FDRE axi_wready_reg
       (.C(pwm_axi_aclk),
        .CE(1'b1),
        .D(axi_wready0),
        .Q(S_AXI_WREADY),
        .R(axi_awready_i_1_n_0));
  LUT5 #(
    .INIT(32'h00020000)) 
    \slv_reg0[15]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[1]),
        .I2(p_0_in[0]),
        .I3(p_0_in[2]),
        .I4(pwm_axi_wstrb[1]),
        .O(p_1_in[15]));
  LUT5 #(
    .INIT(32'h00020000)) 
    \slv_reg0[23]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[1]),
        .I2(p_0_in[0]),
        .I3(p_0_in[2]),
        .I4(pwm_axi_wstrb[2]),
        .O(p_1_in[23]));
  LUT5 #(
    .INIT(32'h00020000)) 
    \slv_reg0[31]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[1]),
        .I2(p_0_in[0]),
        .I3(p_0_in[2]),
        .I4(pwm_axi_wstrb[3]),
        .O(p_1_in[31]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \slv_reg0[31]_i_2 
       (.I0(S_AXI_WREADY),
        .I1(S_AXI_AWREADY),
        .I2(pwm_axi_awvalid),
        .I3(pwm_axi_wvalid),
        .O(slv_reg_wren__0));
  LUT5 #(
    .INIT(32'h00020000)) 
    \slv_reg0[7]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[1]),
        .I2(p_0_in[0]),
        .I3(p_0_in[2]),
        .I4(pwm_axi_wstrb[0]),
        .O(p_1_in[7]));
  FDRE \slv_reg0_reg[0] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[7]),
        .D(pwm_axi_wdata[0]),
        .Q(slv_reg0[0]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[10] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[15]),
        .D(pwm_axi_wdata[10]),
        .Q(slv_reg0[10]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[11] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[15]),
        .D(pwm_axi_wdata[11]),
        .Q(slv_reg0[11]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[12] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[15]),
        .D(pwm_axi_wdata[12]),
        .Q(slv_reg0[12]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[13] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[15]),
        .D(pwm_axi_wdata[13]),
        .Q(slv_reg0[13]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[14] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[15]),
        .D(pwm_axi_wdata[14]),
        .Q(slv_reg0[14]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[15] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[15]),
        .D(pwm_axi_wdata[15]),
        .Q(slv_reg0[15]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[16] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[23]),
        .D(pwm_axi_wdata[16]),
        .Q(slv_reg0[16]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[17] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[23]),
        .D(pwm_axi_wdata[17]),
        .Q(slv_reg0[17]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[18] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[23]),
        .D(pwm_axi_wdata[18]),
        .Q(slv_reg0[18]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[19] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[23]),
        .D(pwm_axi_wdata[19]),
        .Q(slv_reg0[19]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[1] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[7]),
        .D(pwm_axi_wdata[1]),
        .Q(slv_reg0[1]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[20] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[23]),
        .D(pwm_axi_wdata[20]),
        .Q(slv_reg0[20]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[21] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[23]),
        .D(pwm_axi_wdata[21]),
        .Q(slv_reg0[21]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[22] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[23]),
        .D(pwm_axi_wdata[22]),
        .Q(slv_reg0[22]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[23] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[23]),
        .D(pwm_axi_wdata[23]),
        .Q(slv_reg0[23]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[24] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[31]),
        .D(pwm_axi_wdata[24]),
        .Q(slv_reg0[24]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[25] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[31]),
        .D(pwm_axi_wdata[25]),
        .Q(slv_reg0[25]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[26] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[31]),
        .D(pwm_axi_wdata[26]),
        .Q(slv_reg0[26]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[27] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[31]),
        .D(pwm_axi_wdata[27]),
        .Q(slv_reg0[27]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[28] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[31]),
        .D(pwm_axi_wdata[28]),
        .Q(slv_reg0[28]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[29] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[31]),
        .D(pwm_axi_wdata[29]),
        .Q(slv_reg0[29]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[2] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[7]),
        .D(pwm_axi_wdata[2]),
        .Q(slv_reg0[2]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[30] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[31]),
        .D(pwm_axi_wdata[30]),
        .Q(slv_reg0[30]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[31] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[31]),
        .D(pwm_axi_wdata[31]),
        .Q(slv_reg0[31]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[3] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[7]),
        .D(pwm_axi_wdata[3]),
        .Q(slv_reg0[3]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[4] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[7]),
        .D(pwm_axi_wdata[4]),
        .Q(slv_reg0[4]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[5] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[7]),
        .D(pwm_axi_wdata[5]),
        .Q(slv_reg0[5]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[6] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[7]),
        .D(pwm_axi_wdata[6]),
        .Q(slv_reg0[6]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[7] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[7]),
        .D(pwm_axi_wdata[7]),
        .Q(slv_reg0[7]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[8] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[15]),
        .D(pwm_axi_wdata[8]),
        .Q(slv_reg0[8]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg0_reg[9] 
       (.C(pwm_axi_aclk),
        .CE(p_1_in[15]),
        .D(pwm_axi_wdata[9]),
        .Q(slv_reg0[9]),
        .R(axi_awready_i_1_n_0));
  LUT5 #(
    .INIT(32'h02000000)) 
    \slv_reg1[15]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[2]),
        .I2(p_0_in[1]),
        .I3(pwm_axi_wstrb[1]),
        .I4(p_0_in[0]),
        .O(\slv_reg1[15]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h02000000)) 
    \slv_reg1[23]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[2]),
        .I2(p_0_in[1]),
        .I3(pwm_axi_wstrb[2]),
        .I4(p_0_in[0]),
        .O(\slv_reg1[23]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h02000000)) 
    \slv_reg1[31]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[2]),
        .I2(p_0_in[1]),
        .I3(pwm_axi_wstrb[3]),
        .I4(p_0_in[0]),
        .O(\slv_reg1[31]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h02000000)) 
    \slv_reg1[7]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[2]),
        .I2(p_0_in[1]),
        .I3(pwm_axi_wstrb[0]),
        .I4(p_0_in[0]),
        .O(\slv_reg1[7]_i_1_n_0 ));
  FDRE \slv_reg1_reg[0] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[0]),
        .Q(slv_reg1[0]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[10] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[10]),
        .Q(slv_reg1[10]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[11] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[11]),
        .Q(slv_reg1[11]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[12] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[12]),
        .Q(slv_reg1[12]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[13] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[13]),
        .Q(slv_reg1[13]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[14] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[14]),
        .Q(slv_reg1[14]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[15] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[15]),
        .Q(slv_reg1[15]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[16] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[16]),
        .Q(slv_reg1[16]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[17] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[17]),
        .Q(slv_reg1[17]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[18] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[18]),
        .Q(slv_reg1[18]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[19] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[19]),
        .Q(slv_reg1[19]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[1] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[1]),
        .Q(slv_reg1[1]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[20] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[20]),
        .Q(slv_reg1[20]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[21] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[21]),
        .Q(slv_reg1[21]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[22] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[22]),
        .Q(slv_reg1[22]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[23] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[23]),
        .Q(slv_reg1[23]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[24] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[24]),
        .Q(slv_reg1[24]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[25] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[25]),
        .Q(slv_reg1[25]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[26] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[26]),
        .Q(slv_reg1[26]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[27] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[27]),
        .Q(slv_reg1[27]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[28] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[28]),
        .Q(slv_reg1[28]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[29] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[29]),
        .Q(slv_reg1[29]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[2] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[2]),
        .Q(slv_reg1[2]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[30] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[30]),
        .Q(slv_reg1[30]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[31] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[31]),
        .Q(slv_reg1[31]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[3] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[3]),
        .Q(slv_reg1[3]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[4] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[4]),
        .Q(slv_reg1[4]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[5] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[5]),
        .Q(slv_reg1[5]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[6] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[6]),
        .Q(slv_reg1[6]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[7] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[7]),
        .Q(slv_reg1[7]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[8] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[8]),
        .Q(slv_reg1[8]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg1_reg[9] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg1[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[9]),
        .Q(slv_reg1[9]),
        .R(axi_awready_i_1_n_0));
  LUT5 #(
    .INIT(32'h02000000)) 
    \slv_reg2[15]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[2]),
        .I2(p_0_in[0]),
        .I3(pwm_axi_wstrb[1]),
        .I4(p_0_in[1]),
        .O(\slv_reg2[15]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h02000000)) 
    \slv_reg2[23]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[2]),
        .I2(p_0_in[0]),
        .I3(pwm_axi_wstrb[2]),
        .I4(p_0_in[1]),
        .O(\slv_reg2[23]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h02000000)) 
    \slv_reg2[31]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[2]),
        .I2(p_0_in[0]),
        .I3(pwm_axi_wstrb[3]),
        .I4(p_0_in[1]),
        .O(\slv_reg2[31]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h02000000)) 
    \slv_reg2[7]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[2]),
        .I2(p_0_in[0]),
        .I3(pwm_axi_wstrb[0]),
        .I4(p_0_in[1]),
        .O(\slv_reg2[7]_i_1_n_0 ));
  FDRE \slv_reg2_reg[0] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[0]),
        .Q(slv_reg2[0]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[10] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[10]),
        .Q(slv_reg2[10]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[11] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[11]),
        .Q(slv_reg2[11]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[12] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[12]),
        .Q(slv_reg2[12]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[13] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[13]),
        .Q(slv_reg2[13]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[14] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[14]),
        .Q(slv_reg2[14]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[15] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[15]),
        .Q(slv_reg2[15]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[16] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[16]),
        .Q(slv_reg2[16]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[17] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[17]),
        .Q(slv_reg2[17]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[18] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[18]),
        .Q(slv_reg2[18]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[19] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[19]),
        .Q(slv_reg2[19]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[1] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[1]),
        .Q(slv_reg2[1]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[20] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[20]),
        .Q(slv_reg2[20]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[21] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[21]),
        .Q(slv_reg2[21]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[22] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[22]),
        .Q(slv_reg2[22]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[23] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[23]),
        .Q(slv_reg2[23]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[24] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[24]),
        .Q(slv_reg2[24]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[25] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[25]),
        .Q(slv_reg2[25]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[26] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[26]),
        .Q(slv_reg2[26]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[27] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[27]),
        .Q(slv_reg2[27]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[28] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[28]),
        .Q(slv_reg2[28]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[29] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[29]),
        .Q(slv_reg2[29]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[2] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[2]),
        .Q(slv_reg2[2]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[30] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[30]),
        .Q(slv_reg2[30]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[31] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[31]),
        .Q(slv_reg2[31]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[3] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[3]),
        .Q(slv_reg2[3]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[4] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[4]),
        .Q(slv_reg2[4]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[5] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[5]),
        .Q(slv_reg2[5]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[6] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[6]),
        .Q(slv_reg2[6]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[7] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[7]),
        .Q(slv_reg2[7]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[8] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[8]),
        .Q(slv_reg2[8]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg2_reg[9] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg2[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[9]),
        .Q(slv_reg2[9]),
        .R(axi_awready_i_1_n_0));
  LUT5 #(
    .INIT(32'h20000000)) 
    \slv_reg3[15]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[2]),
        .I2(p_0_in[1]),
        .I3(p_0_in[0]),
        .I4(pwm_axi_wstrb[1]),
        .O(\slv_reg3[15]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h20000000)) 
    \slv_reg3[23]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[2]),
        .I2(p_0_in[1]),
        .I3(p_0_in[0]),
        .I4(pwm_axi_wstrb[2]),
        .O(\slv_reg3[23]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h20000000)) 
    \slv_reg3[31]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[2]),
        .I2(p_0_in[1]),
        .I3(p_0_in[0]),
        .I4(pwm_axi_wstrb[3]),
        .O(\slv_reg3[31]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h20000000)) 
    \slv_reg3[7]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[2]),
        .I2(p_0_in[1]),
        .I3(p_0_in[0]),
        .I4(pwm_axi_wstrb[0]),
        .O(\slv_reg3[7]_i_1_n_0 ));
  FDRE \slv_reg3_reg[0] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[0]),
        .Q(slv_reg3[0]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[10] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[10]),
        .Q(slv_reg3[10]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[11] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[11]),
        .Q(slv_reg3[11]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[12] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[12]),
        .Q(slv_reg3[12]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[13] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[13]),
        .Q(slv_reg3[13]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[14] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[14]),
        .Q(slv_reg3[14]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[15] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[15]),
        .Q(slv_reg3[15]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[16] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[16]),
        .Q(slv_reg3[16]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[17] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[17]),
        .Q(slv_reg3[17]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[18] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[18]),
        .Q(slv_reg3[18]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[19] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[19]),
        .Q(slv_reg3[19]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[1] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[1]),
        .Q(slv_reg3[1]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[20] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[20]),
        .Q(slv_reg3[20]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[21] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[21]),
        .Q(slv_reg3[21]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[22] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[22]),
        .Q(slv_reg3[22]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[23] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[23]),
        .Q(slv_reg3[23]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[24] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[24]),
        .Q(slv_reg3[24]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[25] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[25]),
        .Q(slv_reg3[25]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[26] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[26]),
        .Q(slv_reg3[26]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[27] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[27]),
        .Q(slv_reg3[27]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[28] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[28]),
        .Q(slv_reg3[28]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[29] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[29]),
        .Q(slv_reg3[29]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[2] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[2]),
        .Q(slv_reg3[2]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[30] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[30]),
        .Q(slv_reg3[30]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[31] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[31]),
        .Q(slv_reg3[31]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[3] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[3]),
        .Q(slv_reg3[3]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[4] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[4]),
        .Q(slv_reg3[4]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[5] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[5]),
        .Q(slv_reg3[5]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[6] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[6]),
        .Q(slv_reg3[6]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[7] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[7]),
        .Q(slv_reg3[7]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[8] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[8]),
        .Q(slv_reg3[8]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg3_reg[9] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg3[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[9]),
        .Q(slv_reg3[9]),
        .R(axi_awready_i_1_n_0));
  LUT5 #(
    .INIT(32'h02000000)) 
    \slv_reg4[15]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[1]),
        .I2(p_0_in[0]),
        .I3(p_0_in[2]),
        .I4(pwm_axi_wstrb[1]),
        .O(\slv_reg4[15]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h02000000)) 
    \slv_reg4[23]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[1]),
        .I2(p_0_in[0]),
        .I3(p_0_in[2]),
        .I4(pwm_axi_wstrb[2]),
        .O(\slv_reg4[23]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h02000000)) 
    \slv_reg4[31]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[1]),
        .I2(p_0_in[0]),
        .I3(p_0_in[2]),
        .I4(pwm_axi_wstrb[3]),
        .O(\slv_reg4[31]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h02000000)) 
    \slv_reg4[7]_i_1 
       (.I0(slv_reg_wren__0),
        .I1(p_0_in[1]),
        .I2(p_0_in[0]),
        .I3(p_0_in[2]),
        .I4(pwm_axi_wstrb[0]),
        .O(\slv_reg4[7]_i_1_n_0 ));
  FDRE \slv_reg4_reg[0] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[0]),
        .Q(slv_reg4[0]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[10] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[10]),
        .Q(slv_reg4[10]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[11] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[11]),
        .Q(slv_reg4[11]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[12] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[12]),
        .Q(slv_reg4[12]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[13] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[13]),
        .Q(slv_reg4[13]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[14] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[14]),
        .Q(slv_reg4[14]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[15] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[15]),
        .Q(slv_reg4[15]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[16] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[16]),
        .Q(slv_reg4[16]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[17] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[17]),
        .Q(slv_reg4[17]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[18] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[18]),
        .Q(slv_reg4[18]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[19] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[19]),
        .Q(slv_reg4[19]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[1] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[1]),
        .Q(slv_reg4[1]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[20] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[20]),
        .Q(slv_reg4[20]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[21] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[21]),
        .Q(slv_reg4[21]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[22] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[22]),
        .Q(slv_reg4[22]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[23] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[23]_i_1_n_0 ),
        .D(pwm_axi_wdata[23]),
        .Q(slv_reg4[23]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[24] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[24]),
        .Q(slv_reg4[24]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[25] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[25]),
        .Q(slv_reg4[25]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[26] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[26]),
        .Q(slv_reg4[26]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[27] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[27]),
        .Q(slv_reg4[27]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[28] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[28]),
        .Q(slv_reg4[28]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[29] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[29]),
        .Q(slv_reg4[29]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[2] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[2]),
        .Q(slv_reg4[2]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[30] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[30]),
        .Q(slv_reg4[30]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[31] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[31]_i_1_n_0 ),
        .D(pwm_axi_wdata[31]),
        .Q(slv_reg4[31]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[3] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[3]),
        .Q(slv_reg4[3]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[4] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[4]),
        .Q(slv_reg4[4]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[5] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[5]),
        .Q(slv_reg4[5]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[6] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[6]),
        .Q(slv_reg4[6]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[7] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[7]_i_1_n_0 ),
        .D(pwm_axi_wdata[7]),
        .Q(slv_reg4[7]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[8] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[8]),
        .Q(slv_reg4[8]),
        .R(axi_awready_i_1_n_0));
  FDRE \slv_reg4_reg[9] 
       (.C(pwm_axi_aclk),
        .CE(\slv_reg4[15]_i_1_n_0 ),
        .D(pwm_axi_wdata[9]),
        .Q(slv_reg4[9]),
        .R(axi_awready_i_1_n_0));
  LUT3 #(
    .INIT(8'h20)) 
    slv_reg_rden
       (.I0(pwm_axi_arvalid),
        .I1(pwm_axi_rvalid),
        .I2(S_AXI_ARREADY),
        .O(slv_reg_rden__0));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
